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micron serial nor flash memory 3v, multiple i/o, 4kb sector erase n25q512a features ? stacked device (two 256mb die) ? spi-compatible serial bus interface ? double transfer rate (dtr) mode ? 2.7C3.6v single supply voltage ? 108 mhz (max) clock frequency supported for all protocols in single transfer rate (str) mode ? 54 mhz (max) clock frequency supported for all protocols in dtr mode ? dual/quad i/o instruction provides increased throughput up to 54 mb/s ? supported protocols C extended spi, dual i/o, and quad i/o C dtr mode supported on all ? execute-in-place (xip) mode for all three protocols C configurable via volatile or nonvolatile registers C enables memory to work in xip mode directly af- ter power-on ? program/erase suspend operations ? available protocols C available read operations C quad or dual output fast read C quad or dual i/o fast read ? flexible to fit application C configurable number of dummy cycles C output buffer configurable ? software reset ? additional reset pin for selected part numbers 1 ? 3-byte and 4-byte addressability mode supported ? 64-byte, user-lockable, one-time programmable (otp) dedicated area ? erase capability C subsector erase 4kb uniform granularity blocks C sector erase 64kb uniform granularity blocks C single die erase ? write protection C software write protection applicable to every 64kb sector via volatile lock bit C hardware write protection: protected area size defined by five nonvolatile bits (bp0, bp1, bp2, bp3, and tb) C additional smart protections, available upon re- quest ? electronic signature C jedec-standard 2-byte signature (ba20h) C unique id code (uid): 17 read-only bytes, including: two additional extended device id bytes to identify device factory options; and cus- tomized factory data (14 bytes) ? minimum 100,000 erase cycles per sector ? more than 20 years data retention ? packages C jedec-standard, all rohs-compliant C v-pdfn-8/8mm x 6mm (also known as son, dfpn, mlp, mlf) C sop2-16/300mils (also known as so16w, so16- wide, soic-16) C t-pbga-24b05/6mm x 8mm (also known as tbga24) note: 1. part numbers: n25q512a83g1240x, n25q512a83gsf40x 512mb, multiple i/o serial flash memory features pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
contents device description ........................................................................................................................................... 6 features ....................................................................................................................................................... 6 3-byte address and 4-byte address modes ..................................................................................................... 6 operating protocols ...................................................................................................................................... 6 xip mode ..................................................................................................................................................... 7 device configurability .................................................................................................................................. 7 signal assignments ........................................................................................................................................... 8 signal descriptions ........................................................................................................................................... 9 memory organization .................................................................................................................................... 11 memory configuration and block diagram .................................................................................................. 11 memory map C 512mb density ....................................................................................................................... 12 device protection ........................................................................................................................................... 13 serial peripheral interface modes .................................................................................................................... 15 spi protocols .................................................................................................................................................. 17 nonvolatile and volatile registers ................................................................................................................... 18 status register ............................................................................................................................................ 19 nonvolatile and volatile configuration registers .......................................................................................... 20 extended address register .......................................................................................................................... 23 enhanced volatile configuration register .................................................................................................... 24 flag status register ..................................................................................................................................... 25 command definitions .................................................................................................................................... 27 read register and write register operations ........................................................................................ 31 read status register or flag status register command ................................................................ 31 read nonvolatile configuration register command ................................................................... 32 read volatile or enhanced volatile configuration register command .................................. 32 read extended address register command ..................................................................................... 33 write status register command ......................................................................................................... 33 write nonvolatile configuration register command ................................................................. 34 write volatile or enhanced volatile configuration register command ................................. 34 write extended address register command ................................................................................... 35 read lock register command .............................................................................................................. 35 write lock register command ............................................................................................................ 37 clear flag status register command ................................................................................................ 38 read identification operations ............................................................................................................... 39 read id and multiple i/o read id commands ...................................................................................... 39 read serial flash discovery parameter command ......................................................................... 40 read memory operations ............................................................................................................................ 44 3-byte address ........................................................................................................................................... 44 4-byte address ........................................................................................................................................... 45 read memory operations timing C single transfer rate ........................................................................... 47 read memory operations timing C double transfer rate ......................................................................... 50 program operations .................................................................................................................................... 53 write operations .......................................................................................................................................... 58 write enable command ......................................................................................................................... 58 write disable command ........................................................................................................................ 58 erase operations .......................................................................................................................................... 60 subsector erase command ................................................................................................................... 60 sector erase command ......................................................................................................................... 60 die erase command ................................................................................................................................ 61 bulk erase command ............................................................................................................................. 62 512mb, multiple i/o serial flash memory features pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
program/erase suspend command ..................................................................................................... 64 program/erase resume command ...................................................................................................... 66 reset operations .......................................................................................................................................... 67 reset enable and reset memory command ........................................................................................ 67 one-time programmable operations ....................................................................................................... 68 read otp array command ...................................................................................................................... 68 program otp array command .............................................................................................................. 68 address mode operations C enter and exit 4-byte address mode ................................................................. 70 enter or exit 4-byte address mode command ................................................................................... 70 enter or exit quad command ................................................................................................................ 70 xip mode ....................................................................................................................................................... 71 activate or terminate xip using volatile configuration register ................................................................... 71 activate or terminate xip using nonvolatile configuration register ............................................................. 71 confirmation bit settings required to activate or terminate xip .................................................................. 72 terminating xip after a controller and memory reset ................................................................................. 73 power-up and power-down ............................................................................................................................ 74 power-up and power-down requirements .................................................................................................. 74 power loss recovery sequence ................................................................................................................... 75 ac reset specifications ................................................................................................................................... 76 absolute ratings and operating conditions ..................................................................................................... 80 dc characteristics and operating conditions .................................................................................................. 82 ac characteristics and operating conditions .................................................................................................. 83 package dimensions ....................................................................................................................................... 85 part number ordering information ................................................................................................................. 88 revision history ............................................................................................................................................. 90 rev. o C 05/13 ............................................................................................................................................. 90 rev. n C 02/13 ............................................................................................................................................. 90 rev. m C 12/12 ............................................................................................................................................ 90 rev. l C 11/12 ............................................................................................................................................. 90 rev. k C 11/12 ............................................................................................................................................. 90 rev. j C 08/12 .............................................................................................................................................. 90 rev. i C 07/12 .............................................................................................................................................. 90 rev. h C 06/12 ............................................................................................................................................. 90 rev. g C 06/12 ............................................................................................................................................. 90 rev. f C 06/12 ............................................................................................................................................. 91 rev. e C 05/12 ............................................................................................................................................. 91 rev. d C 02/12 ............................................................................................................................................. 91 rev. c, preliminary C 11/11 .......................................................................................................................... 91 rev. b C 11/11 ............................................................................................................................................. 91 rev. a C 07/11 ............................................................................................................................................. 91 512mb, multiple i/o serial flash memory features pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
list of figures figure 1: logic diagram ................................................................................................................................... 7 figure 2: 16-pin, plastic small outline C so16 (top view) .................................................................................. 8 figure 3: 24-ball tbga (balls down) ................................................................................................................ 8 figure 4: block diagram ................................................................................................................................ 11 figure 5: bus master and memory devices on the spi bus ............................................................................... 16 figure 6: spi modes ....................................................................................................................................... 16 figure 7: internal configuration register ........................................................................................................ 18 figure 8: upper and lower memory array segments ....................................................................................... 23 figure 9: read register command ............................................................................................................ 32 figure 10: write register command ......................................................................................................... 34 figure 11: read lock register command ................................................................................................. 37 figure 12: write lock register command ............................................................................................... 38 figure 13: read id and multiple i/o read id commands .......................................................................... 40 figure 14: read command ........................................................................................................................... 47 figure 15: fast read command ................................................................................................................... 47 figure 16: dual output fast read command .......................................................................................... 48 figure 17: dual input/output fast read command .............................................................................. 48 figure 18: quad output fast read command ......................................................................................... 49 figure 19: quad input/output fast read command ............................................................................. 49 figure 20: fast read command C dtr ......................................................................................................... 50 figure 21: dual output fast read command C dtr ................................................................................ 51 figure 22: dual input/output fast read command C dtr .................................................................... 51 figure 23: quad output fast read command C dtr ............................................................................... 52 figure 24: quad input/output fast read command C dtr ................................................................... 52 figure 25: page program command .......................................................................................................... 54 figure 26: dual input fast program command ...................................................................................... 55 figure 27: extended dual input fast program command ................................................................... 55 figure 28: quad input fast program command ..................................................................................... 56 figure 29: extended quad input fast program command ................................................................... 57 figure 30: write enable and write disable command sequence ............................................................ 59 figure 31: subsector and sector erase command .................................................................................. 61 figure 32: die erase command ................................................................................................................... 62 figure 33: bulk erase command ................................................................................................................ 64 figure 34: reset enable and reset memory command ........................................................................... 67 figure 35: read otp command .................................................................................................................... 68 figure 36: program otp command ............................................................................................................ 69 figure 37: xip mode directly after power-on .................................................................................................. 72 figure 38: power-up timing .......................................................................................................................... 74 figure 39: reset ac timing during program or erase cycle ........................................................................ 77 figure 40: reset enable ................................................................................................................................. 77 figure 41: serial input timing ........................................................................................................................ 77 figure 42: hold timing .................................................................................................................................. 78 figure 43: output timing .............................................................................................................................. 78 figure 44: v pph timing .................................................................................................................................. 79 figure 45: ac timing input/output reference levels ...................................................................................... 81 figure 46: v-pdfn-8/8mm x 6mm ................................................................................................................. 85 figure 47: sop2-16/300 mils .......................................................................................................................... 86 figure 48: t-pbga-24b05/6mm x 8mm .......................................................................................................... 87 512mb, multiple i/o serial flash memory features pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
list of tables table 1: signal descriptions ............................................................................................................................. 9 table 2: sectors[1023:0] ................................................................................................................................. 12 table 3: data protection using device protocols ............................................................................................. 13 table 4: memory sector protection truth table .............................................................................................. 13 table 5: protected area sizes C upper area ..................................................................................................... 13 table 6: protected area sizes C lower area ...................................................................................................... 14 table 7: spi modes ........................................................................................................................................ 15 table 8: extended, dual, and quad spi protocols ............................................................................................ 17 table 9: status register bit definitions ........................................................................................................... 19 table 10: nonvolatile configuration register bit definitions ........................................................................... 20 table 11: volatile configuration register bit definitions .................................................................................. 21 table 12: sequence of bytes during wrap ....................................................................................................... 22 table 13: supported clock frequencies C str ................................................................................................. 22 table 14: supported clock frequencies C dtr ................................................................................................ 22 table 15: extended address register bit definitions ........................................................................................ 24 table 16: enhanced volatile configuration register bit definitions .................................................................. 24 table 17: flag status register bit definitions .................................................................................................. 25 table 18: command set ................................................................................................................................. 27 table 19: lock register .................................................................................................................................. 35 table 20: data/address lines for read id and multiple i/o read id commands ....................................... 39 table 21: read id data out ............................................................................................................................ 39 table 22: extended device id, first byte ......................................................................................................... 39 table 23: serial flash discovery parameter data structure .............................................................................. 41 table 24: parameter id .................................................................................................................................. 41 table 25: command/address/data lines for read memory commands ....................................................... 44 table 26: command/address/data lines for read memory commands C 4-byte address ............................. 45 table 27: data/address lines for program commands ................................................................................ 53 table 28: suspend parameters ....................................................................................................................... 65 table 29: operations allowed/disallowed during device states ...................................................................... 66 table 30: otp control byte (byte 64) .............................................................................................................. 69 table 31: xip confirmation bit ....................................................................................................................... 72 table 32: effects of running xip in different protocols .................................................................................... 72 table 33: power-up timing and v wi threshold ............................................................................................... 75 table 34: ac reset conditions ...................................................................................................................... 76 table 35: absolute ratings ............................................................................................................................. 80 table 36: operating conditions ...................................................................................................................... 80 table 37: input/output capacitance .............................................................................................................. 80 table 38: ac timing input/output conditions ............................................................................................... 81 table 39: dc current characteristics and operating conditions ...................................................................... 82 table 40: dc voltage characteristics and operating conditions ...................................................................... 82 table 41: ac characteristics and operating conditions ................................................................................... 83 table 42: part number information ................................................................................................................ 88 table 43: package details ............................................................................................................................... 89 512mb, multiple i/o serial flash memory features pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
device description the n25q is a high-performance multiple input/output serial flash memory device manufactured on 65nm nor technology. it features execute-in-place (xip) functionali- ty, advanced write protection mechanisms, and a high-speed spi-compatible bus inter- face. innovative, high-performance, dual and quad input/output instructions enable double or quadruple the transfer bandwidth for read and program operations. features the 512mb n25q stacked device contains two 256mb die. from a user standpoint this stacked device behaves as a monolithic device, except with regard to read memory and erase operations and status polling. the device contains a single chip select (s#); a dual-chip version is also available. contact the factory for more information. the memory is organized as 1024 (64kb) main sectors that are further divided into 16 subsectors each (16,384 subsectors in total). the memory can be erased one 4kb sub- sector at a time, 64kb sectors at a time, or single die (256mb) at a time. the memory can be write protected by software through volatile and nonvolatile pro- tection features, depending on the application needs. the protection granularity is of 64kb (sector granularity) for volatile protections the device has 64 one-time programmable (otp) bytes that can be read and program- med with the read otp and program otp commands. these 64 bytes can also be permanently locked with a program otp command. the device can also pause and resume program and erase cycles by using dedicated program/erase suspend and resume instructions. 3-byte address and 4-byte address modes the device features 3-byte or 4-byte address modes to access memory beyond 128mb. when 4-byte address mode is enabled, all commands requiring an address must be en- tered and exited with a 4-byte address mode command: enter 4-byte address mode command and exit 4-byte address mode command. the 4-byte address mode can also be enabled through the nonvolatile configuration register. see registers for more information. operating protocols the memory can be operated with three different protocols: ? extended spi (standard spi protocol upgraded with dual and quad operations) ? dual i/o spi ? quad i/o spi the standard spi protocol is extended and enhanced by dual and quad operations. in addition, the dual spi and quad spi protocols improve the data access time and throughput of a single i/o device by transmitting commands, addresses, and data across two or four data lines. each protocol contains unique commands to perform read operations in dtr mode. this enables high data throughput while running at lower clock frequencies. 512mb, multiple i/o serial flash memory device description pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
xip mode xip mode requires only an address (no instruction) to output data, improving random access time and eliminating the need to shadow code onto ram for fast execution. nonvolatile configuration register bits can set xip mode as the default mode for appli- cations that must enter xip mode immediately after powering up. all protocols support xip operation. for flexibility, multiple xip entry and exit methods are available. for applications that must enter xip mode immediately after power-up, nonvolatile configuration register bit settings can enable xip as the default mode. device configurability the n25q family offers additional features that are configured through the nonvolatile configuration register for default and/or nonvolatile settings. volatile settings can be configured through the volatile and volatile-enhanced configuration registers. these configurable features include the following: ? number of dummy cycles for the fast read commands ? output buffer impedance ? spi protocol types (extended spi, dual spi, or quad spi) ? required xip mode ? enabling/disabling hold (reset function) ? enabling/disabling wrap mode figure 1: logic diagram nor die 1 nor die 2 v cc c dq1 reset dq0 v ss s# v pp /w#/dq2 hold#/dq3 note: 1. reset functionality is available in devices with a dedicated part number. see part num- ber ordering information for more details. the reset pin is available only for part num- bers n25q512a83g1240x and n25q512a83gsf40x. on these two parts, the additional reset pin must be connected to an external pull-up. 512mb, multiple i/o serial flash memory device description pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
signal assignments figure 2: 16-pin, plastic small outline C so16 (top view) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 c dq0 dnu dnu dnu dnu v ss v pp /dq2 hold#/dq3 v cc dnu dnu dnu dnu s# dq1 note: 1. reset functionality is available in devices with a dedicated part number. see part num- ber ordering information for complete package names and details. figure 3: 24-ball tbga (balls down) a b c d e nc nc nc nc nc nc v cc v pp /dq2 hold#/dq3 nc nc v ss nc dq0 nc nc c s# dq1 nc nc nc nc nc 5 4 3 2 1 note: 1. see part number ordering information for complete package names and details. 512mb, multiple i/o serial flash memory signal assignments pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
signal descriptions the signal description table below is a comprehensive list of signals for the n25 family devices. all signals listed may not be supported on this device. see signal assignments for information specific to this device. table 1: signal descriptions symbol type description c input clock: provides the timing of the serial interface. commands, addresses, or data present at se- rial data inputs are latched on the rising edge of the clock. data is shifted out on the falling edge of the clock. s# input chip select: when s# is high, the device is deselected and dq1 is at high-z. when in exten- ded spi mode, with the device deselected, dq1 is tri-stated. unless an internal program, erase, or write status register cycle is in progress, the device enters standby power mode (not deep power-down mode). driving s# low enables the device, placing it in the active pow- er mode. after power-up, a falling edge on s# is required prior to the start of any command. dq0 input and i/o serial data: transfers data serially into the device. it receives command codes, addresses, and the data to be programmed. values are latched on the rising edge of the clock. dq0 is used for input/output during the following operations: dual output fast read, quad output fast read, dual input/output fast read, and quad input/output fast read. when used for output, data is shifted out on the falling edge of the clock. in dio-spi, dq0 always acts as an input/output. in qio-spi, dq0 always acts as an input/output, with the exception of the program or erase cycle performed with v pp . the device temporarily enters the extended spi protocol and then re- turns to qio-spi as soon as v pp goes low. dq1 output and i/o serial data: transfers data serially out of the device. data is shifted out on the falling edge of the clock. dq1 is used for input/output during the following operations: dual input fast program, quad input fast program, dual input extended fast program, and quad input extended fast program. when used for input, data is latched on the rising edge of the clock. in dio-spi, dq1 always acts as an input/output. in qio-spi, dq1 always acts as an input/output, with the exception of the program or erase cycle performed with the enhanced program supply voltage (v pp ). in this case the device tem- porarily enters the extended spi protocol and then returns to qio-spi as soon as v pp goes low. dq2 input and i/o dq2: when in qio-spi mode or in extended spi mode using quad fast read commands, the signal functions as dq2, providing input/output. all data input drivers are always enabled except when used as an output. micron recommends customers drive the data signals normally (to avoid unnecessary switching current) and float the signals before the memory device drives data on them. dq3 input and i/o dq3: when in quad spi mode or in extended spi mode using quad fast read commands, the signal functions as dq3, providing input/output. hold# is disabled and reset# is disabled if the device is selected. reset# control input reset: this is a hardware reset# signal. when reset# is driven high, the memory is in the normal operating mode. when reset# is driven low, the memory enters reset mode and out- put is high-z. if reset# is driven low while an internal write, program, or erase operation is in progress, data may be lost. 512mb, multiple i/o serial flash memory signal descriptions pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 1: signal descriptions (continued) symbol type description hold# control input hold: pauses any serial communications with the device without deselecting the device. dq1 (output) is high-z. dq0 (input) and the clock are "don't care." to enable hold, the device must be selected with s# driven low. hold# is used for input/output during the following operations: quad output fast read, quad input/output fast read, quad input fast program, and quad input extended fast program. in qio-spi, hold# acts as an i/o (dq3 functionality), and the hold# functionality is disabled when the device is selected. when the device is deselected (s# is high) in parts with reset# functionality, it is possible to reset the device unless this functionality is not disabled by means of dedicated registers bits. the hold# functionality can be disabled using bit 4 of the nvcr or bit 4 of the vecr. on devices that include dtr mode capability, the hold# functionality is disabled as soon as a dtr operation is recognized. w# control input write protect: w# can be used as a protection control input or in qio-spi operations. when in extended spi with single or dual commands, the write protect function is selectable by the voltage range applied to the signal. if voltage range is low (0v to v cc ), the signal acts as a write protection control input. the memory size protected against program or erase opera- tions is locked as specified in the status register block protect bits 3:0. w# is used as an input/output (dq2 functionality) during quad input fast read and quad input/output fast read operations and in qio-spi. v pp power supply voltage: if v pp is in the voltage range of v pph , the signal acts as an additional power supply, as defined in the ac measurement conditions table. during qifp, qiefp, and qio-spi program/erase operations, it is possible to use the addition- al v pp power supply to speed up internal operations. however, to enable this functionality, it is necessary to set bit 3 of the vecr to 0. in this case, v pp is used as an i/o until the end of the operation. after the last input data is shif- ted in, the application should apply v pp voltage to v pp within 200ms to speed up the internal operations. if the v pp voltage is not applied within 200ms, the program/erase operations start at standard speed. the default value of vecr bit 3 is 1, and the v pp functionality for quad i/o modify operations is disabled. v cc power device core power supply: source voltage. v ss ground ground: reference for the v cc supply voltage. dnu C do not use. nc C no connect. 512mb, multiple i/o serial flash memory signal descriptions pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
memory organization memory configuration and block diagram the memory is a stacked device comprised of two 256mb chips. each chip is internally partitioned into two 128mb segments. each page of memory can be individually pro- grammed. bits are programmed from one through zero. the device is subsector, sector, or single 256mb chip erasable, but not page-erasable. bits are erased from zero through one. the memory is configured as 67,108,864 bytes (8 bits each); 1024 sectors (64kb each); 16,384 subsectors (4kb each); and 262,144 pages (256 bytes each); and 64 otp bytes are located outside the main memory array. figure 4: block diagram hold# s# w#/v pp control logic high voltage generator i/o shift register address register and counter 256 byte data buffer 256 bytes (page size) x decoder y decoder c status register 0000000h 03ffffffh 00000ffh 64 otp bytes dq0 dq1 dq2 dq3 512mb, multiple i/o serial flash memory memory organization pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
memory map C 512mb density table 2: sectors[1023:0] sector subsector address range start end 1023 16383 03ff f000h 03ff ffffh ? ? ? 16368 03ff 0000h 03ff 0fffh ? ? ? ? 511 8191 01ff f000h 01ff ffffh ? ? ? 8176 01ff 0000h 01ff 0fffh ? ? ? ? 255 4095 00ff f000h 00ff ffffh ? ? ? 4080 00ff 0000h 00ff 0fffh ? ? ? ? 127 2047 007f f000h 007f ffffh ? ? ? 2032 007f 0000h 007f 0fffh ? ? ? ? 63 1023 003f f000h 003f ffffh ? ? ? 1008 003f 0000h 003f 0fffh ? ? ? ? 0 15 0000 f000h 0000 ffffh ? ? ? 0 0000 0000h 0000 0fffh 512mb, multiple i/o serial flash memory memory map C 512mb density pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
device protection table 3: data protection using device protocols note 1 applies to the entire table protection by: description power-on reset and internal timer protects the device against inadvertent data changes while the power supply is out- side the operating specification. command execution check ensures that the number of clock pulses is a multiple of one byte before executing a program or erase command, or any command that writes to the device registers. write enable operation ensures that commands modifying device data must be preceded by a write enable command, which sets the write enable latch bit in the status register. note: 1. extended, dual, and quad spi protocol functionality ensures that device data is protec- ted from excessive noise. table 4: memory sector protection truth table note 1 applies to the entire table sector lock register memory sector protection status sector lock down bit sector write lock bit 0 0 sector unprotected from program and erase operations. protection status re- versible. 0 1 sector protected from program and erase operations. protection status rever- sible. 1 0 sector unprotected from program and erase operations. protection status not reversible except by power cycle or reset. 1 1 sector protected from program and erase operations. protection status not reversible except by power cycle or reset. note: 1. sector lock register bits are written to when the write to lock register command is executed. the command will not execute unless the sector lock down bit is cleared (see the write to lock register command). table 5: protected area sizes C upper area note 1 applies to the entire table status register content memory content top/ bottom bit bp3 bp2 bp1 bp0 protected area unprotected area 0 0 0 0 0 none all sectors 0 0 0 0 1 sector 1023 sectors (0 to 1022) 0 0 0 1 0 sectors (1022 to 1023) sectors (0 to 1021) 0 0 0 1 1 sectors (1020 to 1023) sectors (0 to 1019) 0 0 1 0 0 sectors (1016 to 1023) sectors (0 to 1015) 0 0 1 0 1 sectors (1008 to 1023) sectors (0 to 1007) 512mb, multiple i/o serial flash memory device protection pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 5: protected area sizes C upper area (continued) note 1 applies to the entire table status register content memory content top/ bottom bit bp3 bp2 bp1 bp0 protected area unprotected area 0 0 1 1 0 sectors (992 to 1023) sectors (0 to 991) 0 0 1 1 1 sectors (960 to 1023) sectors (0 to 959) 0 1 0 0 0 sectors (896 to 1023) sectors (0 to 895) 0 1 0 0 1 sectors (768 to 1023) sectors (0 to 767) 0 1 0 1 0 sectors (512 to 1023) sectors (0 to 511) 0 1 0 1 1 all sectors none 0 1 1 0 0 all sectors none 0 1 1 0 1 all sectors none 0 1 1 1 0 all sectors none 0 1 1 1 1 all sectors none note: 1. see the status register for details on the top/bottom bit and the bp 3:0 bits. table 6: protected area sizes C lower area note 1 applies to the entire table status register content memory content top/ bottom bit bp3 bp2 bp1 bp0 protected area unprotected area 1 0 0 0 0 none all sectors 1 0 0 0 1 sector 0 sectors (1 to 1023) 1 0 0 1 0 sectors (0 to 1) sectors (2 to 1023) 1 0 0 1 1 sectors (0 to 3) sectors (4 to 1023) 1 0 1 0 0 sectors (0 to 7) sectors (8 to 1023) 1 0 1 0 1 sectors (0 to 15) sectors (16 to 1023) 1 0 1 1 0 sectors (0 to 31) sectors (32 to 1023) 1 0 1 1 1 sectors (0 to 63) sectors (64 to 1023) 1 1 0 0 0 sectors (0 to 127) sectors (128 to 1023) 1 1 0 0 1 sectors (0 to 255) sectors (256 to 1023) 1 1 0 1 0 lower half sectors (512 to 1023) 1 1 0 1 1 all sectors none 1 1 1 0 0 all sectors none 1 1 1 0 1 all sectors none 1 1 1 1 0 all sectors none 1 1 1 1 1 all sectors none note: 1. see the status register for details on the top/bottom bit and the bp 3:0 bits. 512mb, multiple i/o serial flash memory device protection pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
serial peripheral interface modes the device can be driven by a microcontroller while its serial peripheral interface is in either of the two modes shown here. the difference between the two modes is the clock polarity when the bus master is in standby mode and not transferring data. input data is latched in on the rising edge of the clock, and output data is available from the falling edge of the clock. table 7: spi modes note 1 applies to the entire table spi modes clock polarity cpol = 0, cpha = 0 c remains at 0 for (cpol = 0, cpha = 0) cpol = 1, cpha = 1 c remains at 1 for (cpol = 1, cpha = 1) note: 1. the listed spi modes are supported in extended, dual, and quad spi protocols. shown below is an example of three memory devices in extended spi protocol in a sim- ple connection to an mcu on an spi bus. because only one device is selected at a time, that one device drives dq1, while the other devices are high-z. resistors ensure the device is not selected if the bus master leaves s# high-z. the bus master might enter a state in which all input/output is high-z simultaneously, such as when the bus master is reset. therefore, the serial clock must be connected to an exter- nal pull-down resistor so that s# is pulled high while the serial clock is pulled low. this ensures that s# and the serial clock are not high simultaneously and that t shch is met. the typical resistor value of 100k , assuming that the time constant r cp (cp = parasitic capacitance of the bus line), is shorter than the time the bus master leaves the spi bus in high-z. example: cp = 50pf, that is r cp = 5 s. the application must ensure that the bus mas- ter never leaves the spi bus high-z for a time period shorter than 5 s. w# and hold# should be driven either high or low, as appropriate. 512mb, multiple i/o serial flash memory serial peripheral interface modes pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 5: bus master and memory devices on the spi bus spi bus master spi memory device sdo sdi sck c dq1 dq0 spi memory device c dq1 dq0 spi memory device c dq1 dq0 s# cs3 cs2 cs1 spi interface: (cpol, cpha) = (0, 0) or (1, 1) w# hold# s# w# hold# s# w# hold# r r r v cc v cc v cc v cc v ss v ss v ss v ss r figure 6: spi modes c c dq0 dq1 cpha 0 1 cpol 0 1 msb msb 512mb, multiple i/o serial flash memory serial peripheral interface modes pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
spi protocols table 8: extended, dual, and quad spi protocols protocol name com- mand input address input data input/output description extended dq0 multiple dq n lines, depending on the command multiple dq n lines, depending on the command device default protocol from the factory. additional com- mands extend the standard spi protocol and enable address or data transmission on multiple dq n lines. dual dq[1:0] dq[1:0] dq[1:0] volatile selectable: when the enhanced volatile configu- ration register bit 6 is set to 0 and bit 7 is set to 1, the de- vice enters the dual spi protocol immediately after the write enhanced volatile configuration register command. the device returns to the default protocol after the next power-on. in addition, the device can return to de- fault protocol using the rescue sequence or through new write enhanced volatile configuration register command, without power-off or power-on. nonvolatile selectable: when nonvolatile configuration register bit 2 is set, the device enters the dual spi protocol after the next power-on. once this register bit is set, the de- vice defaults to the dual spi protocol after all subsequent power-on sequences until the nonvolatile configuration register bit is reset to 1. quad 1 dq[3:0] dq[3:0] dq[3:0] volatile selectable: when the enhanced volatile configu- ration register bit 7 is set to 0, the device enters the quad spi protocol immediately after the write enhanced vol- atile configuration register command. the device re- turns to the default protocol after the next power-on. in ad- dition, the device can return to default protocol using the rescue sequence or through new write enhanced vola- tile configuration register command, without power- off or power-on. nonvolatile selectable: when nonvolatile configuration register bit 3 is set to 0, the device enters the quad spi pro- tocol after the next power-on. once this register bit is set, the device defaults to the quad spi protocol after all subse- quent power-on sequences until the nonvolatile configura- tion register bit is reset to 1. note: 1. in quad spi protocol, all command/address input and data i/o are transmitted on four lines except during a program and erase cycle performed with v pp . in this case, the device enters the extended spi protocol to temporarily allow the application to perform a program/erase suspend operation or to check the write-in-progress bit in the sta- tus register or the program/erase controller bit in the flag status register. then, when v pp goes low, the device returns to the quad spi protocol. 512mb, multiple i/o serial flash memory spi protocols pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
nonvolatile and volatile registers the device features the following volatile and nonvolatile registers that users can access to store device parameters and operating configurations: ? status register ? nonvolatile and volatile configuration registers ? extended address register ? enhanced volatile configuration register ? flag status register ? lock register note: the lock register is defined in read lock register command. the working condition of memory is set by an internal configuration register that is not directly accessible to users. as shown below, parameters in the internal configuration register are loaded from the nonvolatile configuration register during each device boot phase or power-on reset. in this sense, then, the nonvolatile configuration register con- tains the default settings of memory. also, during the life of an application, each time a write volatile or enhanced volatile configuration register command executes to set configuration pa- rameters in these respective registers, these new settings are copied to the internal con- figuration register. therefore, memory settings can be changed in real time. however, at the next power-on reset, the memory boots according to the memory settings defined in the nonvolatile configuration register parameters. figure 7: internal configuration register register download is executed only during the power-on phase or after a reset, overwriting configuration register settings on the internal configuration register. register download is executed after a write volatile or enhanced volatile configuration register command, overwriting configuration register settings on the internal configuration register. nonvolatile configuration register internal configuration register device behavior volatile configuration register and enhanced volatile configuration register 512mb, multiple i/o serial flash memory nonvolatile and volatile registers pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
status register table 9: status register bit definitions note 1 applies to entire table bit name settings description notes 7 status register write enable/disable 0 = enabled 1 = disabled nonvolatile bit: used with the w# signal to enable or dis- able writing to the status register. 3 5 top/bottom 0 = top 1 = bottom nonvolatile bit: determines whether the protected mem- ory area defined by the block protect bits starts from the top or bottom of the memory array. 4 6, 4:2 block protect 3C0 see protected area sizes C upper area and lower area ta- bles in device pro- tection nonvolatile bit: defines memory to be software protec- ted against program or erase operations. when one or more block protect bits is set to 1, a designated memory area is protected from program and erase operations. 4 1 write enable latch 0 = cleared (default) 1 = set volatile bit: the device always powers up with this bit cleared to prevent inadvertent write status register, program, or erase operations. to enable these opera- tions, the write enable operation must be executed first to set this bit. 2, 5 0 write in progress 0 = ready 1 = busy volatile bit: indicates if one of the following command cy- cles is in progress: write status register write nonvolatile configuration register program erase 2, 6 notes: 1. bits can be read from or written to using read status register or write status reg- ister commands, respectively. 2. volatile bits are cleared to 0 by a power cycle or reset. 3. the status register write enable/disable bit, combined with the w#/v pp signal as descri- bed in the signal descriptions, provides hardware data protection for the device as fol- lows: when the enable/disable bit is set to 1, and the w#/v pp signal is driven low, the status register nonvolatile bits become read-only and the write status register oper- ation will not execute. the only way to exit this hardware-protected mode is to drive w#/v pp high. 4. see protected area sizes tables. the die erase command is executed only if all bits are 0. 5. in case of protection error this volatile bit is set and can be reset only by means of a clear flag status register command. 6. program or erase controller bit = not (write in progress bit). 512mb, multiple i/o serial flash memory nonvolatile and volatile registers pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 19 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
nonvolatile and volatile configuration registers table 10: nonvolatile configuration register bit definitions note 1 applies to entire table bit name settings description notes 15:12 number of dummy clock cycles 0000 (identical to 1111) 0001 0010 . . 1101 1110 1111 sets the number of dummy clock cycles subse- quent to all fast read commands. the default setting targets the maximum al- lowed frequency and guarantees backward com- patibility. 2, 3 11:9 xip mode at power-on re- set 000 = xip: fast read 001 = xip: dual output fast read 010 = xip: dual i/o fast read 011 = xip: quad output fast read 100 = xip: quad i/o fast read 101 = reserved 110 = reserved 111 = disabled (default) enables the device to operate in the selected xip mode immediately after power-on reset. 8:6 output driver strength 000 = reserved 001 = 90 ohms 010 = 60 ohms 011 = 45 ohms 100 = reserved 101 = 20 ohms 110 = 15 ohms 111 = 30 (default) optimizes impedance at v cc /2 output voltage. 5 reserved x "don't care." 4 reset/hold 0 = disabled 1 = enabled (default) enables or disables hold or reset. (available on dedicated part numbers.) 3 quad i/o pro- tocol 0 = enabled 1 = disabled (default, extended spi pro- tocol) enables or disables quad i/o protocol. 4 2 dual i/o pro- tocol 0 = enabled 1 = disabled (default, extended spi pro- tocol) enables or disables dual i/o protocol. 4 1 128mb seg- ment select 0 = upper 128mb segment 1 = lower 128mb segment (default) selects a 128mb segment as default for 3b ad- dress operations. see also the extended address register. 0 address bytes 0 = enable 4b address 1 = enable 3b address (default) defines the number of address bytes for a com- mand. notes: 1. settings determine device memory configuration after power-on. the device ships from the factory with all bits erased to 1 (ffffh). the register is read from or written to by read nonvolatile configuration register or write nonvolatile configura- tion register commands, respectively. 512mb, multiple i/o serial flash memory nonvolatile and volatile registers pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 20 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
2. the 0000 and 1111 settings are identical in that they both define the default state, which is the maximum frequency of f c = 108 mhz. this ensures backward compatibility. 3. if the number of dummy clock cycles is insufficient for the operating frequency, the memory reads wrong data. the number of cycles must be set according to and sufficient for the clock frequency, which varies by the type of fast read command, as shown in the supported clock frequencies table. 4. if bits 2 and 3 are both set to 0, the device operates in quad i/o. when bits 2 or 3 are reset to 0, the device operates in dual i/o or quad i/o respectively, after the next power- on. table 11: volatile configuration register bit definitions note 1 applies to entire table bit name settings description notes 7:4 number of dum- my clock cycles 0000 (identical to 1111) 0001 0010 . . 1101 1110 1111 sets the number of dummy clock cycles subsequent to all fast read commands. the default setting targets maximum allowed frequen- cy and guarantees backward compatibility. 2, 3 3 xip 0 1 enables or disables xip. for device part numbers with feature digit equal to 2 or 4, this bit is always "dont care," so the device operates in xip mode without set- ting this bit. 2 reserved x = default 0b = fixed value. 1:0 wrap 00 = 16-byte boundary aligned 16-byte wrap: output data wraps within an aligned 16- byte boundary starting from the address (3-byte or 4- byte) issued after the command code. 4 01 = 32-byte boundary aligned 32-byte wrap: output data wraps within an aligned 32- byte boundary starting from the address (3-byte or 4- byte) issued after the command code. 10 = 64-byte boundary aligned 64-byte wrap: output data wraps within an aligned 64- byte boundary starting from the address (3-byte or 4- byte) issued after the command code. 11 = sequential (default) continuous reading (default): all bytes are read se- quentially. notes: 1. settings determine the device memory configuration upon a change of those settings by the write volatile configuration register command. the register is read from or written to by read volatile configuration register or write volatile configu- ration register commands respectively. 2. the 0000 and 1111 settings are identical in that they both define the default state, which is the maximum frequency of f c = 108 mhz. this ensures backward compatibility. 3. if the number of dummy clock cycles is insufficient for the operating frequency, the memory reads wrong data. the number of cycles must be set according to and be suffi- cient for the clock frequency, which varies by the type of fast read command, as shown in the supported clock frequencies table. 4. see the sequence of bytes during wrap table. 512mb, multiple i/o serial flash memory nonvolatile and volatile registers pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 21 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 12: sequence of bytes during wrap starting address 16-byte wrap 32-byte wrap 64-byte wrap 0 0-1-2- . . . -15-0-1- . . 0-1-2- . . . -31-0-1- . . 0-1-2- . . . -63-0-1- . . 1 1-2- . . . -15-0-1-2- . . 1-2- . . . -31-0-1-2- . . 1-2- . . . -63-0-1-2- . . 15 15-0-1-2-3- . . . -15-0-1- . . 15-16-17- . . . -31-0-1- . . 15-16-17- . . . -63-0-1- . . 31 31-16-17- . . . -31-16-17- . . 31-0-1-2-3- . . . -31-0-1- . . 31-32-33- . . . -63-0-1- . . 63 63-48-49- . . . -63-48-49- . . 63-32-33- . . . -63-32-33- . . 63-0-1- . . . -63-0-1- . . table 13: supported clock frequencies C str note 1 applies to entire table number of dummy clock cycles fast read dual output fast read dual i/o fast read quad output fast read quad i/o fast read 1 90 80 50 43 30 2 100 90 70 60 40 3 108 100 80 75 50 4 108 105 90 90 60 5 108 108 100 100 70 6 108 108 105 105 80 7 108 108 108 108 86 8 108 108 108 108 95 9 108 108 108 108 105 10 108 108 108 108 108 note: 1. values are guaranteed by characterization and not 100% tested in production. table 14: supported clock frequencies C dtr note 1 applies to entire table number of dummy clock cycles fast read dual output fast read dual i/o fast read quad output fast read quad i/o fast read 1 45 40 25 30 15 2 50 45 35 38 20 3 54 50 40 45 25 4 54 53 45 47 30 5 54 54 50 50 35 6 54 54 53 53 40 7 54 54 54 54 43 8 54 54 54 54 48 9 54 54 54 54 53 10 54 54 54 54 54 note: 1. values are guaranteed by characterization and not 100% tested in production. 512mb, multiple i/o serial flash memory nonvolatile and volatile registers pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 22 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
extended address register in the case of 3-byte addressability mode, the device includes an extended address reg- ister that provides a fourth address byte a[31:24], enabling access to memory beyond 128mb. the extended address register bits [1:0] are used to select one of the four 128mb segments of the memory array. figure 8: upper and lower memory array segments a[25:24] = 00 a[25:24] = 01 a[25:24] = 10 a[25:24] = 11 00ffffffh 00000000h 01ffffffh 01000000h 02ffffffh 02000000h 03ffffffh 03000000h the program and erase operations act upon the 128mb segment selected in the ex- tended address register. the read operation begins reading in the selected 128mb segment. it is bound by the 256mb (die segment) to which the 128mb segment belongs. in a continuos read, when the last byte of the die segment selected is read, the next byte output is the first byte of the same die segment; therefore, a download of the whole array is not possible with one read operation. the value of the extended address register does not change when a read operation crosses the selected 128mb boundary. 512mb, multiple i/o serial flash memory nonvolatile and volatile registers pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 23 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 15: extended address register bit definitions note 1 applies to entire table bit name settings description 7 a[31:26] 0 = reserved C 6 5 4 3 2 1 a[25:24] 11 = upper 128mb segment 10 = third 128mb segment 01 = second 128mb segment 00 = lower 128mb segment (default) enable selecting 128mb segmentation. for a[25:24] , the default setting is determined by bit 1 of the non- volatile configuration register. however, this setting can be changed using the write extended ad- dress register command. 0 note: 1. the extended address register is for an application that supports only 3-byte addressing. it extends the device's first three address bytes a[23:0] to a fourth address byte a[31:24] to enable memory access beyond 128mb. the extended address register bits [1:0] are used to select one of the four 128mb segments of the memory array. if 4-byte address- ing is enabled, extended address register settings are ignored. enhanced volatile configuration register table 16: enhanced volatile configuration register bit definitions note 1 applies to entire table bit name settings description notes 7 quad i/o protocol 0 = enabled 1 = disabled (default, extended spi protocol) enables or disables quad i/o protocol. 2 6 dual i/o protocol 0 = enabled 1 = disabled (default, extended spi protocol) enables or disables dual i/o protocol. 2 5 reserved x = default 0b = fixed value. 4 reset/hold 0 = disabled 1 = enabled (default) enables or disables hold or reset. (available on dedicated part numbers.) 3 v pp accelerator 0 = enabled 1 = disabled (default) enables or disables v pp acceleration for quad input fast program and quad input ex- tended fast program operations. 512mb, multiple i/o serial flash memory nonvolatile and volatile registers pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 24 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 16: enhanced volatile configuration register bit definitions (continued) note 1 applies to entire table bit name settings description notes 2:0 output driver strength 000 = reserved 001 = 90 ohms 010 = 60 ohms 011 = 45 ohms 100 = reserved 101 = 20 ohms 110 = 15 ohms 111 = 30 (default) optimizes impedance at v cc /2 output voltage. notes: 1. settings determine the device memory configuration upon a change of those settings by the write enhanced volatile configuration register command. the register is read from or written to in all protocols by read enhanced volatile configuration register or write enhanced volatile configuration register commands, respec- tively. 2. if bits 6 and 7 are both set to 0, the device operates in quad i/o. when either bit 6 or 7 is reset to 0, the device operates in dual i/o or quad i/o respectively following the next write enhanced volatile configuration command. flag status register table 17: flag status register bit definitions note 1 applies to entire table bit name settings description notes 7 program or erase controller 0 = busy 1 = ready status bit: indicates whether one of the following command cycles is in progress: write status register, write nonvolatile configuration register, program, or erase. 2, 5 6 erase suspend 0 = not in effect 1 = in effect status bit: indicates whether an erase operation has been or is going to be suspended. 2 5 erase 0 = clear 1 = failure or protection error error bit: indicates whether an erase operation has succeeded or failed. 3, 4 4 program 0 = clear 1 = failure or protection error error bit: indicates whether a program operation has succeeded or failed; also an attempt to program a 0 to a 1 when v pp = v pph and the data pattern is a multiple of 64 bits. 3, 4 3 v pp 0 = enabled 1 = disabled (default) error bit: indicates an invalid voltage on v pp during a program or erase operation. 3, 4 2 program sus- pend 0 = not in effect 1 = in effect status bit: indicates whether a program operation has been or is going to be suspended. 2 1 protection 0 = clear 1 = failure or protection error error bit: indicates whether an erase or program operation has attempted to modify the protected array sector, or whether a program operation has attemp- ted to access the locked otp space. 3, 4 512mb, multiple i/o serial flash memory nonvolatile and volatile registers pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 25 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 17: flag status register bit definitions (continued) note 1 applies to entire table bit name settings description notes 0 addressing 0 = 3 bytes addressing 1 = 4 bytes addressing status bit: indicates whether 3-byte or 4-byte address mode is enabled. 2 notes: 1. register bits are read by read flag status register command. all bits are volatile. 2. status bits are reset automatically. 3. error bits must be cleared through the clear flag status register command. 4. these error flags are "sticky." they must be cleared through the clear status regis- ter command. 5. program or erase controller bit = not (write in progress bit). 512mb, multiple i/o serial flash memory nonvolatile and volatile registers pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 26 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
command definitions table 18: command set note 1 applies to entire table command code extended dual i/o quad i/o data bytes notes reset operations reset enable 66h yes yes yes 0 2 reset memory 99h identification operations read id 9e/9fh yes no no 1 to 20 2 multiple i/o read id afh no yes yes 1 to 3 2 read serial flash discovery parameter 5ah yes yes yes 1 to 3 read operations read 03h yes no no 1 to 4 fast read 0bh yes yes yes 5 dual output fast read 3bh yes yes no 1 to 5 dual input/output fast read 0bh 3bh bbh yes yes no 5, 11 quad output fast read 6bh yes no yes 1 to 5 quad input/output fast read 0bh 6bh ebh yes no yes 5, 12 fast read C dtr 0dh yes yes yes 1 to 6 dual output fast read C dtr 3dh yes yes no 1 to 6 dual input/output fast read C dtr 0dh 3dh bdh yes yes no 1 to 6 quad output fast read C dtr 6dh yes no yes 1 to 6 quad input/output fast read C dtr 0dh 3dh edh yes no yes 1 to 7 4-byte read 13h yes yes yes 1 to 8 4-byte fast read 0ch 9 4-byte dual output fast read 3ch yes yes no 1 to 9 4-byte dual input/output fast read bch yes yes no 9, 11 4-byte quad output fast read 6ch yes no yes 1 to 9 4-byte quad input/output fast read ech yes no yes 10, 12 write operations 512mb, multiple i/o serial flash memory command definitions pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 27 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 18: command set (continued) note 1 applies to entire table command code extended dual i/o quad i/o data bytes notes write enable 06h yes yes yes 0 2 write disable 04h register operations read status register 05h yes yes yes 1 to 2 write status register 01h 1 2, 13, 15 read lock register e8h yes yes yes 1 to 4 write lock register e5h 1 4, 13 read flag status register 70h yes yes yes 1 to 2 clear flag status register 50h 0 read nonvolatile configuration register b5h yes yes yes 2 2 write nonvolatile configuration register b1h 2, 13, 15 read volatile configuration register 85h yes yes yes 1 to 2 write volatile configuration register 81h 1 2, 13 read enhanced volatile configuration register 65h yes yes yes 1 to 2 write enhanced volatile configuration register 61h 1 2, 13 read extended address register c8h yes yes yes 0 2 write extended address register c5h 2, 16 program operations page program 02h yes yes yes 1 to 256 4, 13, 14 4-byte page program 12h yes yes yes 1 to 256 4, 13, 14, 17 dual input fast program a2h yes yes no 1 to 256 4, 13, 14 extended dual input fast program 02h a2h d2h yes yes no 4, 11, 13, 14 quad input fast program 32h yes no yes 1 to 256 4, 13, 14 4-byte quad input fast program 34h yes no yes 4, 13, 14, 17 extended quad input fast program 02h 32h 12h/38h yes no yes 4, 12, 13, 14, 18 erase operations subsector erase 20h yes yes yes 0 4, 13, 14 4-byte subsector erase 21h 4, 13, 14, 17 512mb, multiple i/o serial flash memory command definitions pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 28 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 18: command set (continued) note 1 applies to entire table command code extended dual i/o quad i/o data bytes notes sector erase d8h yes yes yes 0 4, 13, 14 4-byte sector erase dch 4, 13, 14, 17 die erase c4h yes yes yes 0 4, 13, 14 bulk erase c7h yes yes yes 0 13, 14, 17 program/erase resume 7ah yes yes yes 0 2, 13, 14 program/erase suspend 75h one-time programmable (otp) operations read otp array 4bh yes yes yes 1 to 64 5 program otp array 42h 4, 13, 14 4-byte address mode operations enter 4-byte address mode b7h yes yes yes 0 2, 16 exit 4-byte address mode e9h quad operations enter quad 35h yes yes yes 0 2, 17 exit quad f5h 2, 17 notes: 1. yes in the protocol columns indicates that the command is supported and has the same functionality and command sequence as other commands marked yes . 2. address bytes = 0. dummy clock cycles = 0. 3. address bytes = 3. dummy clock cycles default = 8. 4. address bytes default = 3; address bytes = 4 (extended address). dummy clock cycles = 0. 5. address bytes default = 3; address bytes = 4 (extended address). dummy clock cycles de- fault = 8. dummy clock cycles default = 10 (when quad spi protocol is enabled). dummy clock cycles are configurable by the user. 6. address bytes default = 3; address bytes = 4 (extended address). dummy clock cycles de- fault = 6. dummy clock cycles default = 8 when quad spi protocol is enabled. dummy clock cycles are configurable by the user. 7. address bytes default = 3; address bytes = 4 (extended address). dummy clock cycles de- fault = 8. dummy clock cycles are configurable by the user. 8. address bytes = 4. dummy clock cycles = 0. 9. address bytes = 4. dummy clock cycles default = 8. dummy clock cycles default = 10 (when quad spi protocol is enabled). dummy clock cycles are configurable by the user. 10. address bytes = 4. dummy clock cycles default = 10. dummy clock cycles is configurable by the user. 11. when the device is in dual spi protocol, the command can be entered with any of these three codes. the different codes enable compatibility between dual spi and extended spi protocols. 12. when the device is in quad spi protocol, the command can be entered with any of these three codes. the different codes enable compatibility between quad spi and extended spi protocols. 13. the write enable command must be issued first before this command can be execu- ted. 512mb, multiple i/o serial flash memory command definitions pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 29 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
14. requires the read flag status register command being issued with at least one byte output. (after code, at least 8 clock pulses in extended spi, 4 clock pulses in dual i/o spi, and 2 clock pulses in quad i/o spi.) the cycle is not complete until bit 7 of the flag status register outputs 1. 15. the end of operation can be detected by means of a read flag status register com- mand being issued twice, s# toggled between command execution, and bit 7 of the flag status register outputs 1 both times. 16. the write enable command must be issued first before this command can be execu- ted. not necessary for part numbers n25q512a83gsf40x and n25q512a83g1240x. 17. only available for part numbers n25q512a83gsf40x and n25q512a83g1240x. 18. the code 38h is valid only for part numbers n25q512a83gsf40x and n25q512a83g1240x; the code 12h is valid for the other part numbers. 512mb, multiple i/o serial flash memory command definitions pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 30 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
read register and write register operations read status register or flag status register command to initiate a read status register command, s# is driven low. for extended spi protocol, the command code is input on dq0, and output on dq1. for dual spi proto- col, the command code is input on dq[1:0], and output on dq[1:0]. for quad spi proto- col, the command code is input on dq[3:0], and is output on dq[3:0]. the operation is terminated by driving s# high at any time during data output. the status register can be read continuously and at any time, including during a pro- gram, erase, or write operation. the flag status register can be read continuously and at any time, including during an erase or write operation. if one of these operations is in progress, checking the write in progress bit or program or erase controller bit is recommended before executing the command. the flag status register must be read any time a program, erase, or suspend/ resume command is issued, or after a reset command while device is busy. the cycle is not complete until bit 7 of the flag status register outputs 1. refer to command defi- nitions for more information. the end of operations such as power-up, write status register, and write non- volatile configuration register can be detected by means of a read flag sta- tus register command being issued twice to poll the flag status register for both die, s# toggled between command execution, and bit 7 of the flag status register outputs 1 both times. 512mb, multiple i/o serial flash memory read register and write register operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 31 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 9: read register command high-z dq1 7 8 9 10 11 12 13 14 15 0 c msb dq0 lsb command 3 4 5 6 7 0 c msb dq[1:0] lsb command msb d out d out d out d out d out lsb extended msb d out d out d out d out d out lsb d out d out d out d out dual quad 1 2 3 0 c msb dq[3:0] lsb command msb d out d out d out lsb dont care notes: 1. supports all read register commands except read lock register. 2. a read nonvolatile configuration register operation will output data starting from the least significant byte. read nonvolatile configuration register command to execute a read nonvolatile configuration register command, s# is driv- en low. for extended spi protocol, the command code is input on dq0, and output on dq1. for dual spi protocol, the command code is input on dq[1:0], and output on dq[1:0]. for quad spi protocol, the command code is input on dq[3:0], and is output on dq[3:0]. the operation is terminated by driving s# high at any time during data output. the nonvolatile configuration register can be read continuously. after all 16 bits of the register have been read, a 0 is output. all reserved fields output a value of 1. read volatile or enhanced volatile configuration register command to execute a read volatile configuration register command or a read en- hanced volatile configuration register command, s# is driven low. for ex- tended spi protocol, the command code is input on dq0, and output on dq1. for dual spi protocol, the command code is input on dq[1:0], and output on dq[1:0]. for quad spi protocol, the command code is input on dq[3:0], and is output on dq[3:0]. the op- eration is terminated by driving s# high at any time during data output. when the register is read continuously, the same byte is output repeatedly. 512mb, multiple i/o serial flash memory read register and write register operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 32 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
read extended address register command to initiate a read extended address register command, s# is driven low. for extended spi protocol, the command code is input on dq0, and output on dq1. for dual spi protocol, the command code is input on dq[1:0], and output on dq[1:0]. for quad spi protocol, the command code is input on dq[3:0], and is output on dq[3:0]. the operation is terminated by driving s# high at any time during data output. when the register is read continuously, the same byte is output repeatedly. write status register command to issue a write status register command, the write enable command must be executed to set the write enable latch bit to 1. s# is driven low and held low until the eighth bit of the last data byte has been latched in, after which it must be driven high. for extended spi protocol, the command code is input on dq0, followed by the data bytes. for dual spi protocol, the command code is input on dq[1:0], followed by the da- ta bytes. for quad spi protocol, the command code is input on dq[3:0], followed by the data bytes. when s# is driven high, the operation, which is self-timed, is initiated; its duration is t w. this command is used to write new values to status register bits 7:2, enabling software data protection. the status register can also be combined with the w#/v pp signal to provide hardware data protection. the write status register command has no ef- fect on status register bits 1:0. when the operation is in progress, the program or erase controller bit of the flag status register is set to 0. to obtain the operation status, the flag status register must be polled twice, with s# toggled twice in between commands. when the operation completes, the program or erase controller bit is cleared to 1. the end of operation can be detected when the flag status register outputs the program or erase controller bit to 1 both times. when the maximum time achieved (see ac characteristics and operating conditions), polling the flag status register twice is not required. 512mb, multiple i/o serial flash memory read register and write register operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 33 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 10: write register command 7 8 9 10 11 12 13 14 15 0 c msb dq0 lsb command 3 4 5 6 7 0 c msb dq[1:0] lsb command msb d in d in d in d in d in lsb extended msb lsb d in d in d in d in d in d in d in d in dual quad 1 2 3 0 c msb dq[3:0] lsb command msb d in d in d in lsb d in notes: 1. supports all write register commands except write lock register. 2. a write nonvolatile configuration register operation requires data being sent starting from least significant byte. for this command, the data in consists of two bytes. write nonvolatile configuration register command to execute the write nonvolatile configuration register command, the write enable command must be executed to set the write enable latch bit to 1. s# is driven low and held low until the 16th bit of the last data byte has been latched in, after which it must be driven high. for extended spi protocol, the command code is input on dq0, followed by two data bytes. for dual spi protocol, the command code is input on dq[1:0], followed by the data bytes. for quad spi protocol, the command code is input on dq[3:0], followed by the data bytes. when s# is driven high, the operation, which is self-timed, is initiated; its duration is t wnvcr. when the operation is in progress, the program or erase controller bit of the flag status register is set to 0. to obtain the operation status, the flag status register must be polled twice, with s# toggled twice in between commands. when the operation completes, the program or erase controller bit is cleared to 1. the end of operation can be detected when the flag status register outputs the program or erase controller bit to 1 both times. when the maximum time achieved (see ac characteristics and operating conditions), polling the flag status register twice is not required. write volatile or enhanced volatile configuration register command to execute a write volatile configuration register command or a write enhanced volatile configuration register command, the write enable command must be executed to set the write enable latch bit to 1. s# is driven low and held low until the eighth bit of the last data byte has been latched in, after which it must be driven high. for extended spi protocol, the command code is input on dq0, 512mb, multiple i/o serial flash memory read register and write register operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 34 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
followed by the data bytes. for dual spi protocol, the command code is input on dq[1:0], followed by the data bytes. for quad spi protocol, the command code is input on dq[3:0], followed by the data bytes. because register bits are volatile, change to the bits is immediate. after the data is latch- ed in, s# must be driven high. reserved bits are not affected by this command. write extended address register command to initiate a write extended address register command, the write enable command must be executed to set the write enable latch bit to 1. note: the write enable command must not be executed for part numbers n25q512a83gsf40x and n25q512a83g1240x. s# is driven low and held low until the eighth bit of the last data byte has been latch- ed in, after which it must be driven high. the command code is input on dq0, fol- lowed by the data bytes. for dual spi protocol, the command code is input on dq[1:0], followed by the data bytes. for quad spi protocol, the command code is input on dq[3:0], followed by the data bytes. because register bits are volatile, change to the bits is immediate. after the data is latch- ed in, s# must be driven high. reserved bits are not affected by this command. read lock register command to execute the read lock register command, s# is driven low. for extended spi protocol, the command code is input on dq0, followed by address bytes that point to a location in the sector. for dual spi protocol, the command code is input on dq[1:0]. for quad spi protocol, the command code is input on dq[3:0]. each address bit is latched in during the rising edge of the clock. for extended spi protocol, data is shifted out on dq1 at a maximum frequency f c during the falling edge of the clock. for dual spi proto- col, data is shifted out on dq[1:0], and for qual spi protocol, data is shifted out on dq[3:0]. the operation is terminated by driving s# high at any time during data out- put. when the register is read continuously, the same byte is output repeatedly. any read lock register command that is executed while an erase, program, or write cy- cle is in progress is rejected with no affect on the cycle in progress. table 19: lock register note 1 applies to entire table bit name settings description 7:2 reserved 0 bit values are 0. 1 write lock down 0 = cleared (default) 1 = set volatile bit: the device always powers-up with this bit cleared, which means sector lock down and sector write lock bits can be set. when this bit set, neither of the lock register bits can be written to until the next power cycle. 512mb, multiple i/o serial flash memory read register and write register operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 35 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 19: lock register (continued) note 1 applies to entire table bit name settings description 0 sector write lock 0 = cleared (default) 1 = set volatile bit: the device always powers-up with this bit cleared, which means that program and erase operations in this sector can be executed and sector content modified. when this bit is set, program and erase operations in this sector will not be executed. note: 1. sector lock register bits 1:0 are written to by the write lock register command. the command will not execute unless the sector lock down bit is cleared. 512mb, multiple i/o serial flash memory read register and write register operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 36 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 11: read lock register command msb dq[0] lsb command a[max] a[min] 7 8 c x 0 c 3 4 c x 0 c msb dq[1:0] lsb command a[max] a[min] msb d out d out d out d out d out lsb 1 2 c x 0 c msb dq[3:0] lsb command a[max] a[min] msb d out d out d out lsb extended dual quad high-z dq1 msb d out d out d out d out d out lsb d out d out d out d out dont care note: 1. for extended spi protocol, c x = 7 + (a[max] + 1). for dual spi protocol, c x = 3 + ((a[max] + 1)/2). for quad spi protocol, c x = 1 + ((a[max] + 1)/4). write lock register command to initiate the write lock register command, the write enable command must be executed to set the write enable latch bit to 1. s# is driven low and held low until the eighth bit of the last data byte has been latched in, after which it must be driven high. the command code is input on dqn, followed by address bytes that point to a location in the sector, and then one data byte that contains the desired settings for lock register bits 0 and 1. when execution is complete, the write enable latch bit is cleared within t shsl2 and no error bits are set. because lock register bits are volatile, change to the bits is immediate. write lock register can be executed when an erase suspend operation is in ef- fect. after the data is latched in, s# must be driven high. 512mb, multiple i/o serial flash memory read register and write register operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 37 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 12: write lock register command 7 8 c x 0 c msb dq[0] lsb command a[max] a[min] msb d in d in d in d in d in lsb d in d in d in d in 3 4 c x 0 c msb dq[1:0] lsb command a[max] a[min] msb d in d in d in d in d in lsb 1 2 c x 0 c msb dq[3:0] lsb command a[max] a[min] msb d in d in d in lsb extended dual quad note: 1. for extended spi protocol, c x = 7 + (a[max] + 1). for dual spi protocol, c x = 3 + ((a[max] + 1)/2). for quad spi protocol, c x = 1 + ((a[max] + 1)/4). clear flag status register command to execute the clear flag status register command and clear the error bits (erase, program, and protection), s# is driven low. for extended spi protocol, the com- mand code is input on dq0. for dual spi protocol, the command code is input on dq[1:0]. for quad spi protocol, the command code is input on dq[3:0]. the operation is terminated by driving s# high at any time. 512mb, multiple i/o serial flash memory read register and write register operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 38 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
read identification operations read id and multiple i/o read id commands to execute the read id or multiple i/o read id commands, s# is driven low and the command code is input on dq n . the device outputs the information shown in the tables below. if an erase or program cycle is in progress when the command is exe- cuted, the command is not decoded and the command cycle in progress is not affected. when s# is driven high, the device goes to standby. the operation is terminated by driving s# high at any time during data output. table 20: data/address lines for read id and multiple i/o read id commands command name data in data out unique id is output extended dual quad read id dq0 dq0 yes yes no no multiple i/o read id dq[3:0] dq[1:0] no no yes yes note: 1. yes in the protocol columns indicates that the command is supported and has the same functionality and command sequence as other commands marked yes . table 21: read id data out size (bytes) name content value assigned by 1 manufacturer id 20h jedec 2 device id memory type bah manufacturer memory capacity 20h (512mb) 17 unique id 1 byte: length of data to follow 10h factory 2 bytes: extended device id and device configuration information id and information such as uniform architecture, and hold or reset functionality 14 bytes: customized factory data optional note: 1. the 17 bytes of information in the unique id is read by the read id command, but can- not be read by the multiple i/o read id command. table 22: extended device id, first byte bit 7 bit 6 bit 5 1 bit 4 2 bit 3 bit 2 bit 1 bit 0 reserved reserved 1 = alternate bp scheme 0 = standard bp scheme volatile configuration register bit setting: 0 = micron xip 1 = basic xip hold#/reset#: 0 = hold 1 = reset addressing: 0 = by byte architecture: 00 = uniform notes: 1. for alternate bp scheme information, contact the factory. 2. for more information, contact the factory. 512mb, multiple i/o serial flash memory read identification operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 39 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 13: read id and multiple i/o read id commands uid device identification manufacturer identification high-z dq1 msb msb d out d out d out d out lsb lsb 7 8 15 16 32 31 0 c msb dq0 lsb command msb d out d out lsb extended dual quad dont care 3 4 7 8 15 0 c msb dq[1:0] lsb command device identification manufacturer identification msb msb d out d out d out d out lsb lsb 1 2 3 4 7 0 c msb dq[3:0] lsb command device identification manufacturer identification msb msb d out d out d out d out lsb lsb note: 1. the read id command is represented by the extended spi protocol timing shown first. the multiple i/o read id command is represented by the dual and quad spi protocols are shown below extended spi protocol. read serial flash discovery parameter command to execute read serial flash discovery parameter command, s# is driven low. the command code is input on dq0, followed by three address bytes and eight dummy clock cycles (address is always 3 bytes, even if the device is configured to work in 4-byte address mode). the device outputs the information starting from the specified address. when the 2048-byte boundary is reached, the data output wraps to address 0 of the serial flash discovery parameter table. the operation is terminated by driving s# high at any time during data output. the operation always executes in continuous mode so the read burst wrap setting in the volatile configuration register does not apply. 512mb, multiple i/o serial flash memory read identification operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 40 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 23: serial flash discovery parameter data structure compliant with jedec standard jc-42.4 1775.03 description address (byte mode) address (bit) data serial flash discoverable parameters signature 00h 7:0 53h 01h 15:08 46h 02h 23:16 44h 03h 31:24 50h serial flash discoverable parameters minor revision 04h 7:0 00h major revision 05h 15:8 01h number of parameter headers 06h 7:0 00h reserved 07h 15:8 ffh parameter id (0) jedec-defined parameter table 08h 7:0 00h parameter minor revision 09h 15:8 00h major revision 0ah 23:16 01h parameter length (dw) 0bh 31:24 09h parameter table pointer 0ch 7:0 30h 0dh 15:8 00h 0eh 23:16 00h reserved 0fh 31:24 ffh table 24: parameter id description byte address bits 512mb data minimum block/sector erase sizes 30h 1:0 01b write granularity 2 1 write enable command required for writing to volatile status reg- isters 3 0 write enable command selected for writing to volatile status regis- ters 4 0 reserved 7:5 111b 4kb erase command 31h 7:0 20h 512mb, multiple i/o serial flash memory read identification operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 41 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 24: parameter id (continued) description byte address bits 512mb data supports dual output fast read operation (single input address, dual output) 32h 0 1 number of address bytes used (3-byte or 4-byte) for array read, write, and erase commands 2:1 01b supports double transfer rate clocking 3 1 supports dual input/output fast read operation (dual input ad- dress, dual output) 4 1 supports quad input/output fast read operation (quad input address, quad output) 5 1 supports quad output fast read operation (single input address, quad output) 6 1 reserved 7 1 reserved 33h 7:0 ffh flash size (bits) 34h 7:0 ffh 35h 7:0 ffh 36h 7:0 ffh 37h 7:0 1fh number of dummy clock cycles required before valid output from quad input/output fast read operation 38h 4:0 01001b number of xip confirmation bits for quad input/output fast read operation 7:5 001b command code for quad input/output fast read operation 39h 7:0 ebh number of dummy clock cycles required before valid output from quad output fast read operation 3ah 4:0 00111b number of xip confirmation bits for quad output fast read op- eration 7:5 001b command code for quad output fast read operation 3bh 7:0 6bh number of dummy clock cycles required before valid output from dual output fast read operation 3ch 4:0 00111b number of xip confirmation bits for dual output fast read oper- ation 7:5 001b command code for dual output fast read operation 3dh 7:0 3bh number of dummy clock cycles required before valid output from dual input/output fast read operation 3eh 4:0 00111b number of xip confirmation bits for dual input/output fast read 7:5 001b command code for dual input/output fast read operation 3fh 7:0 bbh 512mb, multiple i/o serial flash memory read identification operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 42 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 24: parameter id (continued) description byte address bits 512mb data supports fast read operation in dual spi protocol 40h 0 1 reserved 3:1 111b supports fast read operation in quad spi protocol 4 1 reserved 7:5 111b reserved 43:41h ffffffh ffffffh reserved 45:44h ffffh ffffh number of dummy clock cycles required before valid output from fast read operation in dual spi protocol 46h 4:0 00111b number of xip confirmation bits for fast read operation in dual spi protocol 7:5 001b command code for fast read operation in dual spi protocol 47h 7:0 bbh reserved 49:48h ffffh ffffh number of dummy clock cycles required before valid output from fast read operation in quad spi protocol 4ah 4:0 01001b number of xip confirmation bits for fast read operation in quad spi protocol 7:5 001b command code for fast read operation in quad spi protocol 4bh 7:0 ebh sector type 1 size (4k) 4ch 7:0 0ch sector type 1 command code (4k) 4dh 7:0 20h sector type 2 size (64kb) 4eh 7:0 10h sector type 2 command code 64kb) 4fh 7:0 d8h sector type 3 size (not present) 50h 7:0 00h sector type 3 size (not present) 51h 7:0 00h sector type 4 size (not present) 52h 7:0 00h sector type 4 size (not present) 53h 7:0 00h 512mb, multiple i/o serial flash memory read identification operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 43 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
read memory operations the device supports default reading and writing to an a[max:min] of a[23:0] (3-byte address). reading and writing to an a[max:min] of a[31:0] (4-byte address) is also supported. se- lection of the 3-byte or 4-byte address range can be enabled in two ways: through the nonvolatile configuration register or through the enable 4-byte address mode/ exit 4-byte address mode commands. further details for these settings and com- mands are in the respective register and command sections of the data sheet. after any read command is executed, the device will output data from the selected ad- dress in the die. after a die boundary is reached, the device will start reading again from the beginning of the same 256mb die. a complete device reading is completed by executing read twice. 3-byte address to execute read memory commands, s# is driven low. the command code is input on dq n , followed by input on dq n of three address bytes. each address bit is latched in during the rising edge of the clock. the addressed byte can be at any location, and the address automatically increments to the next address after each byte of data is shifted out; therefore, a die can be read with a single command. the operation is terminated by driving s# high at any time during data output. table 25: command/address/data lines for read memory commands note 1 applies to entire table command name read fast read dual output fast read dual input/output fast read quad output fast read quad input/output fast read str mode 03 0b 3b bb 6b eb dtr mode C 0d 3d bd 6d ed extended spi protocol supported yes yes yes yes yes yes command input dq0 dq0 dq0 dq0 dq0 dq0 address input dq0 dq0 dq0 dq[1:0] dq0 dq[3:0] data output dq1 dq1 dq[1:0] dq[1:0] dq[3:0] dq[3:0] dual spi protocol supported no yes yes yes no no command input C dq[1:0] dq[1:0] dq[1:0] C C address input C dq[1:0] dq[1:0] dq[1:0] C C data output C dq[1:0] dq[1:0] dq[1:0] C C quad spi protocol supported no yes no no yes yes command input C dq[3:0] C C dq[3:0] dq[3:0] address input C dq[3:0] C C dq[3:0] dq[3:0] 512mb, multiple i/o serial flash memory read memory operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 44 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 25: command/address/data lines for read memory commands (continued) note 1 applies to entire table command name read fast read dual output fast read dual input/output fast read quad output fast read quad input/output fast read str mode 03 0b 3b bb 6b eb dtr mode C 0d 3d bd 6d ed data output C dq[3:0] C C dq[3:0] dq[3:0] notes: 1. yes in the "supported' row for each protocol indicates that the command in that col- umn is supported; when supported, a command's functionality is identical for the entire column regardless of the protocol. for example, a fast read functions the same for all three protocols even though its data is input/output differently depending on the pro- tocol. 2. fast read is similar to read, but requires dummy clock cycles following the address bytes and can operate at a higher frequency ( f c). 4-byte address to execute 4-byte read memory commands, s# is driven low. the command code is input on dq n , followed by input on dq n of four address bytes. each address bit is latched in during the rising edge of the clock. the addressed byte can be at any location, and the address automatically increments to the next address after each byte of data is shifted out; therefore, a die can be read with a single command. the operation is termi- nated by driving s# high at any time during data output. table 26: command/address/data lines for read memory commands C 4-byte address notes 1 and 2 apply to entire table command name (4-byte address) read fast read dual output fast read dual input/output fast read quad output fast read quad input/output fast read str mode 03/13 0b/0c 3b/3c bb/bc 6b/6c eb/ec dtr mode C 0d 3d bd 6d ed extended spi protocol supported yes yes yes yes yes yes command input dq0 dq0 dq0 dq0 dq0 dq0 address input dq0 dq0 dq0 dq[1:0] dq0 dq[3:0] data output dq1 dq1 dq[1:0] dq[1:0] dq[3:0] dq[3:0] dual spi protocol supported no yes yes yes no no command input C dq[1:0] dq[1:0] dq[1:0] C C address input C dq[1:0] dq[1:0] dq[1:0] C C data output C dq[1:0] dq[1:0] dq[1:0] C C 512mb, multiple i/o serial flash memory read memory operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 45 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 26: command/address/data lines for read memory commands C 4-byte address (contin- ued) notes 1 and 2 apply to entire table command name (4-byte address) read fast read dual output fast read dual input/output fast read quad output fast read quad input/output fast read str mode 03/13 0b/0c 3b/3c bb/bc 6b/6c eb/ec dtr mode C 0d 3d bd 6d ed quad spi protocol supported no yes no no yes yes command input C dq[3:0] C C dq[3:0] dq[3:0] address input C dq[3:0] C C dq[3:0] dq[3:0] data output C dq[3:0] C C dq[3:0] dq[3:0] notes: 1. yes in the "supported' row for each protocol indicates that the command in that col- umn is supported; when supported, a command's functionality is identical for the entire column regardless of the protocol. for example, a fast read functions the same for all three protocols even though its data is input/output differently depending on the pro- tocol. 2. command codes 13, 0c, 3c, bc, 6c, and ec do not need to be set up in the addressing mode; they will work directly in 4-byte addressing mode. 3. a 4-byte fast read command is similar to 4-byte read operation, but requires dum- my clock cycles following the address bytes and can operate at a higher frequency ( f c). 512mb, multiple i/o serial flash memory read memory operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 46 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 14: read command dont care msb dq[0] lsb command a[max] a[min] 7 8 c x 0 c extended high-z dq1 msb d out d out d out d out d out lsb d out d out d out d out note: 1. c x = 7 + (a[max] + 1). read memory operations timing C single transfer rate figure 15: fast read command 7 8 c x 0 c msb dq0 lsb command a[max] a[min] 3 4 c x 0 c msb dq[1:0] lsb command a[max] a[min] msb d out d out d out d out d out lsb dummy cycles 1 2 c x 0 c msb dq[3:0] lsb command a[max] a[min] msb d out d out d out lsb dummy cycles extended msb d out d out d out d out d out lsb d out d out d out d out dummy cycles dual quad dq1 high-z dont care note: 1. for extended protocol, c x = 7 + (a[max] + 1). for dual protocol, c x = 3 + (a[max] + 1)/2. for quad protocol, c x = 1 + (a[max] + 1)/4. 512mb, multiple i/o serial flash memory read memory operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 47 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 16: dual output fast read command 7 8 c x 0 c msb dq0 lsb command d out lsb dq1 d out a[max] high-z a[min] d out msb d out d out d out d out d out d out d out dummy cycles notes: 1. c x = 7 + (a[max] + 1). 2. shown here is the dual output fast read timing for the extended spi protocol. the dual timing shown for the fast read command is the equivalent of the dual output fast read timing for the dual spi protocol. figure 17: dual input/output fast read command 7 8 c x 0 c msb dq0 lsb command d out lsb dq1 d out high-z a[min] d out msb d out d out d out d out d out d out d out a[max] dummy cycles notes: 1. c x = 7 + (a[max] + 1)/2. 2. shown here is the dual input/output fast read timing for the extended spi proto- col. the dual timing shown for the fast read command is the equivalent of the dual input/output fast read timing for the dual spi protocol. 512mb, multiple i/o serial flash memory read memory operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 48 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 18: quad output fast read command dummy cycles 7 8 c x 0 c msb dq0 lsb command d out lsb dq[2:1] d out a[max] high-z a[min] d out d out d out d out dq3 d out 1 msb d out d out notes: 1. c x = 7 + (a[max] + 1). 2. shown here is the quad output fast read timing for the extended spi protocol. the quad timing shown for the fast read command is the equivalent of the quad out- put fast read timing for the quad spi protocol. figure 19: quad input/output fast read command dummy cycles 7 8 c x 0 c msb dq0 lsb command d out lsb dq[2:1] d out high-z a[min] d out d out d out d out dq3 d out 1 msb d out d out a[max] notes: 1. c x = 7 + (a[max] + 1)/4. 2. shown here is the quad input/output fast read timing for the extended spi proto- col. the quad timing shown for the fast read command is the equivalent of the quad input/output fast read timing for the quad spi protocol. 512mb, multiple i/o serial flash memory read memory operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 49 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
read memory operations timing C double transfer rate figure 20: fast read command C dtr 7 8 c x 0 c msb dq0 lsb command a[max] a[min] 3 4 c x 0 c msb dq[1:0] lsb command a[max] a[min] msb lsb dummy cycles 1 2 c x 0 c msb dq[3:0] lsb command a[max] a[min] msb lsb dummy cycles extended msb lsb dummy cycles dual quad dq1 high-z dont care d out d out d out d out d out d out d out d out d out d out d out d out d out d out d out d out d out d out d out d out d out d out d out d out d out d out d out d out note: 1. for extended protocol, c x = 7 + (a[max] + 1)/2. for dual protocol, c x = 3 + (a[max] + 1)/4. for quad protocol, c x = 1 + (a[max] + 1)/8. 512mb, multiple i/o serial flash memory read memory operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 50 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 21: dual output fast read command C dtr 7 8 c x 0 c msb dq0 lsb command lsb dq1 a[max] high-z a[min] msb dummy cycles d out d out d out d out d out d out d out d out d out d out d out d out d out d out d out d out notes: 1. c x = 7 + (a[max] + 1)/2. 2. shown here is the dual output fast read timing for the extended spi protocol. the dual timing shown for the fast read command is the equivalent of the dual output fast read timing for the dual spi protocol. figure 22: dual input/output fast read command C dtr 7 8 c x 0 c msb dq0 lsb command d out lsb dq1 d out high-z a[min] d out msb d out d out d out d out d out d out d out d out d out d out d out d out d out a[max] dummy cycles notes: 1. c x = 7 + (a[max] + 1)/4. 2. shown here is the dual input/output fast read timing for the extended spi proto- col. the dual timing shown for the fast read command is the equivalent of the dual input/output fast read timing for the dual spi protocol. 512mb, multiple i/o serial flash memory read memory operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 51 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 23: quad output fast read command C dtr dummy cycles 7 8 c x 0 c msb dq0 lsb command lsb dq[2:1] a[max] high-z a[min] dq3 1 msb d out d out d out d out d out d out d out d out d out d out d out d out notes: 1. c x = 7 + (a[max] + 1)/2. 2. shown here is the quad output fast read timing for the extended spi protocol. the quad timing shown for the fast read command is the equivalent of the quad out- put fast read timing for the quad spi protocol. figure 24: quad input/output fast read command C dtr dummy cycles 7 8 c x 0 c msb dq0 lsb command lsb dq[2:1] high-z a[min] dq3 1 msb a[max] d out d out d out d out d out d out d out d out d out d out d out d out notes: 1. c x = 7 + (a[max] + 1)/8. 2. shown here is the quad input/output fast read timing for the extended spi proto- col. the quad timing shown for the fast read command is the equivalent of the quad input/output fast read timing for the quad spi protocol. 512mb, multiple i/o serial flash memory read memory operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 52 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
program operations program commands are initiated by first executing the write enable command to set the write enable latch bit to 1. s# is then driven low and held low until the eighth bit of the last data byte has been latched in, after which it must be driven high. the command code is input on dq0, followed by input on dq[n] of address bytes and at least one data byte. each address bit is latched in during the rising edge of the clock. when s# is driven high, the operation, which is self-timed, is initiated; its duration is t pp. if the bits of the least significant address, which is the starting address, are not all zero, all data transmitted beyond the end of the current page is programmed from the start- ing address of the same page. if the number of bytes sent to the device exceed the maxi- mum page size, previously latched data is discarded and only the last maximum page- size number of data bytes are guaranteed to be programmed correctly within the same page. if the number of bytes sent to the device is less than the maximum page size, they are correctly programmed at the specified addresses without any effect on the other bytes of the same page. when the operation is in progress, the program or erase controller bit of the flag status register is set to 0. the write enable latch bit is cleared to 0, whether the operation is successful or not. the status register and flag status register can be polled for the opera- tion status. the operation is considered complete after bit 7 of the flag status register outputs 1 with at least one byte output. when the operation completes, the program or erase controller bit is cleared to 1. if the operation times out, the write enable latch bit is reset and the program fail bit is set to 1. if s# is not driven high, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. when a command is applied to a protected sector, the command is not executed, the write enable latch bit remains set to 1, and flag status register bits 1 and 4 are set. note that the flag status register must be polled even if operation times out. table 27: data/address lines for program commands note 1 applies to entire table command name data in address in extended dual quad page program dq0 dq0 yes yes yes dual input fast program dq[1:0] dq0 yes yes no extended dual input fast program dq[1:0] dq[1:0] yes yes no quad input fast program dq[3:0] dq0 yes no yes extended quad input fast program dq[3:0] dq[3:0] yes no yes note: 1. yes in the protocol columns indicates that the command is supported and has the same functionality and command sequence as other commands marked yes . 512mb, multiple i/o serial flash memory program operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 53 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 25: page program command 7 8 c x 0 c msb dq[0] lsb command a[max] a[min] msb d in d in d in d in d in lsb d in d in d in d in 3 4 c x 0 c msb dq[1:0] lsb command a[max] a[min] msb d in d in d in d in d in lsb 1 2 c x 0 c msb dq[3:0] lsb command a[max] a[min] msb d in d in d in lsb extended dual quad note: 1. for extended spi protocol, c x = 7 + (a[max] + 1). for dual spi protocol, c x = 3 + (a[max] + 1)/2. for quad spi protocol, c x = 1 + (a[max] + 1)/4. 512mb, multiple i/o serial flash memory program operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 54 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 26: dual input fast program command extended dual 3 4 c x 0 c msb dq[1:0] lsb command d in lsb a[max] a[min] msb d in d in d in d in 7 8 c x 0 c msb dq0 lsb command d in lsb dq1 d in a[max] high-z a[min] d in msb d in d in d in d in d in d in d in note: 1. for extended spi protocol, c x = 7 + (a[max] + 1). for dual spi protocol, c x = 3 + (a[max] + 1)/2. figure 27: extended dual input fast program command extended dual 3 4 c x 0 c msb dq[1:0] lsb command d in lsb a[max] a[min] msb d in d in d in d in 7 8 c x 0 c msb dq0 lsb command d in lsb dq1 d in high-z a[min] a[max] d in msb d in d in d in d in d in d in d in note: 1. for extended spi protocol, c x = 7 + (a[max] + 1)/2. for dual spi protocol, c x = 3 + (a[max] + 1)/2. 512mb, multiple i/o serial flash memory program operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 55 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 28: quad input fast program command 7 8 c x 0 c msb dq0 lsb command d in lsb dq[3:1] d in a[max] high-z a[min] d in msb d in d in d in extended quad 1 2 c x 0 c msb dq[3:0] lsb command d in lsb a[max] a[min] msb d in d in note: 1. for extended spi protocol, c x = 7 + (a[max] + 1)/4. for quad spi protocol, c x = 1 + (a[max] + 1)/4. 512mb, multiple i/o serial flash memory program operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 56 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 29: extended quad input fast program command 7 8 c x 0 c msb dq0 lsb command d in lsb dq[2:1] d in high-z a[min] a[max] d in d in d in d in dq3 d in 1 msb d in d in extended quad 1 2 c x 0 c msb dq[3:0] lsb command d in lsb a[max] a[min] msb d in d in note: 1. for extended spi protocol, c x = 7 + (a[max] + 1)/4. for quad spi protocol, c x = 1 + (a[max] + 1)/4. 512mb, multiple i/o serial flash memory program operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 57 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
write operations write enable command the write enable operation sets the write enable latch bit. to execute a write ena- ble command, s# is driven low and held low until the eighth bit of the command code has been latched in, after which it must be driven high. the command code is input on dq0 for extended spi protocol, on dq[1:0] for dual spi protocol, and on dq[3:0] for quad spi protocol. the write enable latch bit must be set before every program, erase, write, enter 4-byte address mode, and exit 4-byte address mode command. if s# is not driven high after the command code has been latched in, the command is not execu- ted, flag status register error bits are not set, and the write enable latch remains cleared to its default setting of 0. write disable command the write disable operation clears the write enable latch bit. to execute a write disable command, s# is driven low and held low until the eighth bit of the com- mand code has been latched in, after which it must be driven high. the command code is input on dq0 for extended spi protocol, on dq[1:0] for dual spi protocol, and on dq[3:0] for quad spi protocol. if s# is not driven high after the command code has been latched in, the command is not executed, flag status register error bits are not set, and the write enable latch re- mains set to 1. note: in case of a protection error, write disable will not clear the write enable latch. in this situation, a clear flag status register command must be issued to clear both flags. 512mb, multiple i/o serial flash memory write operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 58 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 30: write enable and write disable command sequence dq[0] msb lsb dual dont care command bits dq[0] 0 1 2 4 5 3 7 6 c extended high-z dq1 msb lsb 0 0 0 0 0 0 1 1 command bits s# s# 0 0 1 0 msb 1 0 c lsb dq[1] dq[2] quad command bits s# 0 0 dq[3] 0 0 dq[0] 0 0 1 1 dq[1] 0 0 0 1 1 2 0 c 3 note: 1. shown here is the write enable command code, which is 06h or 0000 0110 binary. the write disable command sequence is identical, except the write disable command code is 04h or 0000 0100 binary. 512mb, multiple i/o serial flash memory write operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 59 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
erase operations when the operation is in progress, the program or erase controller bit of the flag status register is set to 0. the flag status register must be polled for the operation status. when the operation completes, that bit is cleared to 1. note that the flag status register must be polled even if operation times out. subsector erase command to execute the subsector erase command (and set the selected subsector bits to ffh), the write enable command must be issued to set the write enable latch bit to 1. s# is driven low and held low until the eighth bit of the last data byte has been latched in, after which it must be driven high. the command code is input on dq0, followed by address bytes; any address within the subsector is valid. each address bit is latched in during the rising edge of the clock. when s# is driven high, the operation, which is self-timed, is initiated; its duration is t sse. the operation can be suspended and resumed by the program/erase suspend and program/erase resume commands, respectively. if the write enable latch bit is not set, the device ignores the subsector erase com- mand and no error bits are set to indicate operation failure. when the operation is in progress, the program or erase controller bit is set to 0. the write enable latch bit is cleared to 0, whether the operation is successful or not. the sta- tus register and flag status register can be polled for the operation status. the operation is considered complete once bit 7 of the flag status register outputs 1 with at least one byte output. when the operation completes, the program or erase controller bit is cleared to 1. if the operation times out, the write enable latch bit is reset and the erase error bit is set to 1. if s# is not driven high, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. when a command is applied to a protected subsector, the command is not executed. instead, the write enable latch bit remains set to 1, and flag status register bits 1 and 5 are set. sector erase command to execute the sector erase command (and set selected sector bits to ffh), the write enable command must be issued to set the write enable latch bit to 1. s# is driven low and held low until the eighth bit of the last data byte has been latched in, after which it must be driven high. the command code is input on dq0, followed by address bytes; any address within the sector is valid. each address bit is latched in dur- ing the rising edge of the clock. when s# is driven high, the operation, which is self- timed, is initiated; its duration is t se. the operation can be suspended and resumed by the program/erase suspend and program/erase resume commands, respec- tively. if the write enable latch bit is not set, the device ignores the sector erase command and no error bits are set to indicate operation failure. when the operation is in progress, the program or erase controller bit is set to 0. the write enable latch bit is cleared to 0, whether the operation is successful or not. the sta- tus register and flag status register can be polled for the operation status. the operation is considered complete once bit 7 of the flag status register outputs 1 with at least one 512mb, multiple i/o serial flash memory erase operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 60 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
byte output. when the operation completes, the program or erase controller bit is cleared to 1. if the operation times out, the write enable latch bit is reset and erase error bit is set to 1. if s# is not driven high, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. when a command is applied to a protected sector, the command is not executed. instead, the write enable latch bit re- mains set to 1, and flag status register bits 1 and 5 are set. figure 31: subsector and sector erase command 7 8 c x 0 c msb dq0 lsb command a[max] a[min] 3 4 c x 0 c msb dq0[1:0] lsb command a[max] a[min] 1 2 c x 0 c msb dq0[3:0] lsb command a[max] a[min] extended dual quad note: 1. for extended spi protocol, c x = 7 + (a[max] + 1). for dual spi protocol, c x = 3 + (a[max] + 1)/2. for quad spi protocol, c x = 1 + (a[max] + 1)/4. die erase command to initiate the die erase command, the write enable command must be issued to set the write enable latch bit to 1. s# is driven low and held low until the eighth bit of the last data byte has been latched in, after which it must be driven high. the com- mand code is input on dq0, followed by address bytes; any address within the single 256mb die is valid. each address bit is latched in during the rising edge of the clock. when s# is driven high, the operation, which is self-timed, is initiated; its duration is t dse. if the write enable latch bit is not set, the device ignores the die erase command and no error bits are set to indicate operation failure. when the operation is in progress, the program or erase controller bit is set to 0. the write enable latch bit is cleared to 0, whether the operation is successful or not. the sta- tus register and flag status register can be polled for the operation status. the operation is considered complete once bit 7 of the flag status register outputs 1 with at least one 512mb, multiple i/o serial flash memory erase operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 61 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
byte output. when the operation completes, the program or erase controller bit is cleared to 1. the command is not executed if any sector is locked. instead, the write enable latch bit remains set to 1, and flag status register bits 1 and 5 are set. figure 32: die erase command 7 8 c x 0 c msb dq0 lsb command a[max] a[min] 3 4 c x 0 c msb dq0[1:0] lsb command a[max] a[min] 1 2 c x 0 c msb dq0[3:0] lsb command a[max] a[min] extended dual quad note: 1. for extended spi protocol, c x = 7 + (a[max] + 1). for dual spi protocol, c x = 3 + (a[max] + 1)/2. for quad spi protocol, c x = 1 + (a[max] + 1)/4. bulk erase command the bulk erase command is valid for part numbers n25q512a83gsf40x and n25q512a83g1240x. to initiate the bulk erase command, the write enable com- mand must be issued to set the write enable latch bit to 1. s# is driven low and held low until the eighth bit of the last data byte has been latched in, after which it must be driven high. the command code is input on dq0. when s# is driven high, the opera- tion, which is self-timed, is initiated; its duration is t be. if the write enable latch bit is not set, the device ignores the sector erase command and no error bits are set to indicate operation failure. when the operation is in progress, the write in progress bit is set to 1 and the write ena- ble latch bit is cleared to 0, whether the operation is successful or not. the status regis- ter and flag status register can be polled for the operation status. when the operation completes, the write in progress bit is cleared to 0. if the operation times out, the write enable latch bit is reset and erase error bit is set to 1. if s# is not driven high, the command is not executed, the flag status register error bits are not set, and the write enable latch remains set to 1. 512mb, multiple i/o serial flash memory erase operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 62 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
the command is not executed if any sector is locked. instead, the write enable latch bit remains set to 1, and flag status register bits 1 and 5 are set. 512mb, multiple i/o serial flash memory erase operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 63 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 33: bulk erase command 7 0 c msb dq0 lsb command 3 0 c msb dq0[1:0] lsb command 1 0 c msb dq0[3:0] lsb command extended dual quad program/erase suspend command to initiate the program/erase suspend command, s# is driven low. the com- mand code is input on dq0. the operation is terminated by the program/erase re- sume command. program/erase suspend command enables the memory controller to interrupt and suspend an array program or erase operation within the program/erase latency. if a suspend command is issued during a program operation, then the flag status register bit 2 is set to 1. after erase/program latency time, the flag status register bit 7 is also set to 1, but the device is considered in suspended state once bit 7 of the flag status register outputs 1 with at least one byte output. in the suspended state, the device is waiting for any operation. (see the operations allowed/disallowed during device states table.) if a suspend command is issued during an erase operation, then the flag status regis- ter bit 6 is set to 1. after erase/program latency time, the flag status register bit 7 is also set to 1, but the device is considered in suspended state once bit 7 of the flag status reg- ister outputs 1 with at least one byte output. in the suspended state, the device is wait- ing for any operation. (see the operations allowed/disallowed during device states ta- ble.) if the time remaining to complete the operation is less than the suspend latency, the de- vice completes the operation and clears the flag status register bits 2 or 6, as applicable. because the suspend state is volatile, if there is a power cycle, the suspend state infor- mation is lost and the flag status register powers up as 80h. during an erase suspend operation, a program or read operation is possible in any sector except the one in a suspended state. reading from a sector that is in a sus- pended state will output indeterminate data. the device ignores a program com- 512mb, multiple i/o serial flash memory erase operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 64 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
mand to a sector that is in an erase suspend state; it also sets the flag status register bit 4 to 1, program failure/protection error, and leaves the write enable latch bit unchanged. the commands allowed during an erase suspend state are shown in the operations al- lowed/disallowed during device states table. when the erase resumes, it does not check the new lock status of the write lock register command. during a program suspend operation, a read operation is possible in any page ex- cept the one in a suspended state. reading from a page that is in a suspended state will output indeterminate data. the commands allowed during a program suspend state in- clude the write volatile configuration register command and the write enhanced volatile configuration register command. it is possible to nest a program/erase suspend operation inside a program/ erase suspend operation just once. issue an erase command and suspend it. then issue a program command and suspend it also. with the two operations suspended, the next program/erase resume command resumes the latter operation, and a sec- ond program/erase resume command resumes the former (or first) operation. table 28: suspend parameters parameter condition typ max units notes erase to suspend sector erase or erase resume to erase suspend 700 C s 1 program to suspend program resume to program suspend 5 C s 1 subsector erase to sus- pend subsector erase or subsector erase resume to erase sus- pend 50 C s 1 suspend latency program 7 C s 2 suspend latency subsector erase 15 C s 2 suspend latency erase 15 C s 3 notes: 1. timing is not internally controlled. 2. any read command accepted. 3. any command except the following are accepted: sector, subsector, or die erase; write status register; write nonvolatile configuration register; and pro- gram otp. 512mb, multiple i/o serial flash memory erase operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 65 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 29: operations allowed/disallowed during device states note 1 applies to entire table operation standby state program or erase state subsector erase suspend or program suspend state erase suspend state notes read yes no yes yes 2 program yes no no yes/no 3 erase yes no no no 4 write yes no no no 5 write yes no yes yes 6 read yes yes yes yes 7 suspend no yes no no 8 notes: 1. the device can be in only one state at a time. depending on the state of the device, some operations are allowed (yes) and others are not (no). for example, when the de- vice is in the standby state, all operations except suspend are allowed in any sector. for all device states except the erase suspend state, if an operation is allowed or disallowed in one sector, it is allowed or disallowed in all other sectors. in the erase suspend state, a program operation is allowed in any sector except the one in which an erase opera- tion has been suspended. 2. all read operations except read status register and read flag register. when is- sued to a sector or subsector that is simultaneously in an erase suspend state, the read operation is accepted, but the data output is not guaranteed until the erase has comple- ted. 3. all program operations except program otp. in the erase suspend state, a program operation is allowed in any sector (yes) except the sector (no) in which an erase opera- tion has been suspended. 4. applies to the sector erase or subsector erase operation. 5. applies to the following operations: write status register, write nonvolatile configuration register, program otp, and die erase. 6. applies to the write volatile configuration register, write enhanced vola- tile configuration register, write enable, write disable, clear flag status register, write extended address register, enter 4-byte extended address register, exit 4-byte extended address register, or write lock register opera- tion. 7. applies to the read status register or read flag status register operation. 8. applies to the program suspend or erase suspend operation. program/erase resume command to initiate the program/erase resume command, s# is driven low. the command code is input on dq0. the operation is terminated by driving s# high. when this command is executed, the status register write in progress bit is set to 1, and the flag status register program erase controller bit is set to 0. this command is ignored if the device is not in a suspended state. when the operation is in progress, the program or erase controller bit of the flag status register is set to 0. the flag status register must be polled for the operation status. when the operation completes, that bit is cleared to 1. note that the flag status register must be polled even if operation times out. 512mb, multiple i/o serial flash memory erase operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 66 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
reset operations reset enable and reset memory command to reset the device, the reset enable command must be followed by the reset memory command. to execute each command, s# is driven low. the command code is input on dq0. a minimum de-selection time of t shsl2 must come between the re- set enable and reset memory commands or a reset is not guaranteed. when these two commands are executed and s# is driven high, the device enters a power-on reset condition. a time of t shsl3 is required before the device can be re-selected by driving s# low. it is recommended that the device exit xip mode before executing these two commands to initiate a reset. all volatile lock bits, the volatile configuration register, the enhanced volatile configura- tion register, and the extended address register are reset to the power-on reset default condition. the power-on reset condition depends on settings in the nonvolatile config- uration register. if a reset is initiated while a write, program, or erase operation is in progress or suspended, the operation is aborted and data may be corrupted. reset is effective once bit 7 of the flag status register outputs 1 with at least one byte output. a reset enable command is not accepted in the cases of write status register and write non- volatile configuration register operations. figure 34: reset enable and reset memory command c s# dq0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 reset enable reset memory note: 1. the number of lines and rate for transmission varies with extended, dual, or quad spi. 512mb, multiple i/o serial flash memory reset operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 67 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
one-time programmable operations read otp array command to initiate a read otp array command, s# is driven low. the command code is in- put on dq0, followed by address bytes and dummy clock cycles. each address bit is latched in during the rising edge of c. data is shifted out on dq1, beginning from the specified address and at a maximum frequency of f c (max) on the falling edge of the clock. the address increments automatically to the next address after each byte of data is shifted out. there is no rollover mechanism; therefore, if read continuously, after lo- cation 0x40, the device continues to output data at location 0x40. the operation is ter- minated by driving s# high at any time during data output. figure 35: read otp command 7 8 c x 0 c msb dq0 lsb command a[max] a[min] 3 4 c x 0 c msb dq[1:0] lsb command a[max] a[min] msb d out d out d out d out d out lsb dummy cycles 1 2 c x 0 c msb dq[3:0] lsb command a[max] a[min] msb d out d out d out lsb dummy cycles extended msb d out d out d out d out d out lsb d out d out d out d out dummy cycles dual quad dq1 high-z dont care note: 1. for extended spi protocol, c x = 7 + (a[max] + 1). for dual spi protocol, c x = 3 + (a[max] + 1)/2. for quad spi protocol, c x = 1 + (a[max] + 1)/4. program otp array command to initiate the program otp array command, the write enable command must be issued to set the write enable latch bit to 1; otherwise, the program otp array command is ignored and flag status register bits are not set. s# is driven low and held low until the eighth bit of the last data byte has been latched in, after which it must be driven high. the command code is input on dq0, followed by address bytes and at least one data byte. each address bit is latched in during the rising edge of the clock. when s# is driven high, the operation, which is self-timed, is initiated; its duration is t potp. there is no rollover mechanism; therefore, after a maximum of 65 bytes are latched in the subsequent bytes are discarded. 512mb, multiple i/o serial flash memory one-time programmable operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 68 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
program otp array programs, at most, 64 bytes to the otp memory area and one otp control byte. when the operation is in progress, the write in progress bit is set to 1. the write enable latch bit is cleared to 0, whether the operation is successful or not, and the status register and flag status register can be polled for the operation status. when the operation completes, the write in progress bit is cleared to 0. if the operation times out, the write enable latch bit is reset and the program fail bit is set to 1. if s# is not driven high, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. the operation is considered complete once bit 7 of the flag status register outputs 1 with at least one byte output. the otp control byte (byte 64) is used to permanently lock the otp memory array. table 30: otp control byte (byte 64) bit name settings description 0 otp control byte 0 = locked 1 = unlocked (default) used to permanently lock the 64-byte otp array. when bit 0 = 1, the 64-byte otp array can be programmed. when bit 0 = 0, the 64-byte otp array is read only. once bit 0 has been programmed to 0, it can no longer be changed to 1. program otp array is ignored, the write enable latch bit remains set, and flag status register bits 1 and 4 are set. figure 36: program otp command 7 8 c x 0 c msb dq[0] lsb command a[max] a[min] msb d in d in d in d in d in lsb d in d in d in d in 3 4 c x 0 c msb dq[1:0] lsb command a[max] a[min] msb d in d in d in d in d in lsb 1 2 c x 0 c msb dq[3:0] lsb command a[max] a[min] msb d in d in d in lsb extended dual quad note: 1. for extended spi protocol, c x = 7 + (a[max] + 1). for dual spi protocol, c x = 3 + (a[max] + 1)/2. for quad spi protocol, c x = 1 + (a[max] + 1)/4. 512mb, multiple i/o serial flash memory one-time programmable operations pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 69 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
address mode operations C enter and exit 4-byte address mode enter or exit 4-byte address mode command both enter 4-byte address mode and exit 4-byte address mode commands share the same requirements. to enter or exit the 4-byte address mode, the write enable command must be execu- ted to set the write enable latch bit to 1. note: the write enable command must not be executed on the n25q512a83g1241e and n25q512a83g1241f devices. s# must be driven low. the command must be input on dq n . the effect of the com- mand is immediate; after the command has been executed, the write enable latch bit is cleared to 0. the default address mode is three bytes, and the device returns to the default upon exit- ing the 4-byte address mode. enter or exit quad command the enter or exit quad (qpi) command is available only on the n25q512a83g1241e and n25q512a83g1241f devices. to initiate this command, s# must be driven low, and the command must be input on dq n . the effect of the command is immediate. note: the write enable command must not be executed before this command. 512mb, multiple i/o serial flash memory address mode operations C enter and exit 4-byte address mode pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 70 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
xip mode execute-in-place (xip) mode allows the memory to be read by sending an address to the device and then receiving the data on one, two, or four pins in parallel, depending on the customer requirements. xip mode offers maximum flexibility to the application, saves instruction overhead, and reduces random access time. activate or terminate xip using volatile configuration register applications that boot in spi and must switch to xip use the volatile configuration reg- ister. xip provides faster memory read operations by requiring only an address to exe- cute, rather than a command code and an address. to activate xip requires two steps. first, enable xip by setting volatile configuration reg- ister bit 3 to 0. next, drive the xip confirmation bit to 0 during the next fast read op- eration. xip is then active. once in xip, any command that occurs after s# is toggled re- quires only address bits to execute; a command code is not necessary, and device oper- ations use the spi protocol that is enabled. xip is terminated by driving the xip confir- mation bit to 1. the device automatically resets volatile configuration register bit 3 to 1. note: for devices with basic xip, indicated by a part number feature set digit of 2 or 4, it is not necessary to set the volatile configuration register bit 3 to 0 to enable xip. instead, it is enabled by setting the xip confirmation bit to 0 during the first dummy clock cycle after any fast read command. activate or terminate xip using nonvolatile configuration register applications that must boot directly in xip use the nonvolatile configuration register. to enable a device to power-up in xip using the nonvolatile configuration register, set non- volatile configuration register bits [11:9]. settings vary according to protocol, as ex- plained in the nonvolatile configuration register section. because the device boots di- rectly in xip, after the power cycle, no command code is necessary. xip is terminated by driving the xip confirmation bit to 1. 512mb, multiple i/o serial flash memory xip mode pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 71 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 37: xip mode directly after power-on c v cc s# dq0 dq[3:1] d out xb d out d out d out d out d out d out d out d out d out 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 t vsi (<100) nvcr check: xip enabled dummy cycles mode 3 mode 0 a[max] msb a[min] lsb note: 1. xb is the xip confirmation bit and should be set as follows: 0 to keep xip state; 1 to exit xip mode and return to standard read mode. confirmation bit settings required to activate or terminate xip the xip confirmation bit setting activates or terminates xip after it has been enabled or disabled. this bit is the value on dq0 during the first dummy clock cycle in the fast read operation. in dual i/o xip mode, the value of dq1 during the first dummy clock cycle after the addresses is always "don't care." in quad i/o xip mode, the values of dq3, dq2, and dq1 during the first dummy clock cycle after the addresses are always "don't care." table 31: xip confirmation bit bit value description 0 activates xip: while this bit is 0, xip remains activated. 1 terminates xip: when this bit is set to 1, xip is terminated and the device returns to spi. table 32: effects of running xip in different protocols protocol effect extended i/o and dual i/o in a device with a dedicated part number where rst# is enabled, a low pulse on that pin resets xip and the device to the state it was in previous to the last power-up, as defined by the nonvolatile configuration register. dual i/o values of dq1 during the first dummy clock cycle are "don't care." 512mb, multiple i/o serial flash memory xip mode pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 72 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 32: effects of running xip in different protocols (continued) protocol effect quad i/o 1 values of dq[3:1] during the first dummy clock cycle are "don't care." in a de- vice with a dedicated part number, it is only possible to reset memory when the device is deselected. note: 1. in a device with a dedicated part number where rst# is enabled, a low pulse on that pin resets xip and the device to the state it was in previous to the last power-up, as de- fined by the nonvolatile configuration register only when the device is deselected. terminating xip after a controller and memory reset the system controller and the device can become out of synchronization if, during the life of the application, the system controller is reset without the device being reset. in such a case, the controller can reset the memory to power-on reset if the memory has reset functionality. (reset is available in devices with a dedicated part number.) ? 7 clock cycles within s# low (s# becomes high before 8th clock cycle) ? + 9 clock cycles within s# low (s# becomes high before 10th clock cycle) ? + 13 clock cycles within s# low (s# becomes high before 14th clock cycle) ? + 17 clock cycles within s# low (s# becomes high before 18th clock cycle) ? + 25 clock cycles within s# low (s# becomes high before 26th clock cycle) ? + 33 clock cycles within s# low (s# becomes high before 34th clock cycle) these sequences cause the controller to set the xip confirmation bit to 1, thereby termi- nating xip. however, it does not reset the device or interrupt program/erase opera- tions that may be in progress. after terminating xip, the controller must execute reset enable and reset memory to implement a software reset and reset the device. 512mb, multiple i/o serial flash memory xip mode pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 73 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
power-up and power-down power-up and power-down requirements at power-up and power-down, the device must not be selected; that is, s# must follow the voltage applied on v cc until v cc reaches the correct values: v cc,min at power-up and v ss at power-down. to avoid data corruption and inadvertent write operations during power-up, a power- on reset circuit is included. the logic inside the device is held to reset while v cc is less than the power-on reset threshold voltage shown here; all operations are disabled, and the device does not respond to any instruction. during a standard power-up phase, the device ignores all commands except read status register and read flag status register. these operations can be used to check the memory internal state. after power-up, the device is in standby power mode; the write enable latch bit is reset; the write in progress bit is reset; and the lock registers are configured as: (write lock bit, lock down bit) = (0,0). normal precautions must be taken for supply line decoupling to stabilize the v cc sup- ply. each device in a system should have the v cc line decoupled by a suitable capacitor (typically 100nf) close to the package pins. at power-down, when v cc drops from the operating voltage to below the power-on-reset threshold voltage shown here, all opera- tions are disabled and the device does not respond to any command. when the operation is in progress, the program or erase controller bit of the status reg- ister is set to 0. to obtain the operation status, the flag status register must be polled twice, with s# toggled twice in between commands. when the operation completes, the program or erase controller bit is cleared to 1. the cycle is complete after the flag status register outputs the program or erase controller bit to 1 both times. note: if power-down occurs while a write, program, or erase cycle is in progress, data corruption may result. v pph must be applied only when v cc is stable and in the v cc,min to v cc,max voltage range. figure 38: power-up timing v cc v cc,min v wi chip reset chip selection not allowed polling allowed t vtp t vtw = t vtr time v cc,max device fully accessible spi protocol starting protocol defined by nvcr wip = 1 wel = 0 wip = 0 wel = 0 512mb, multiple i/o serial flash memory power-up and power-down pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 74 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 33: power-up timing and v wi threshold note 1 applies to entire table symbol parameter min max unit t vtr v cc,min to read C 150 s t vtw v cc,min to device fully accessible C 150 s v wi write inhibit voltage 1.5 2.5 v t vtp v cc,min to polling allowed C 100 s note: 1. parameters listed are characterized only. power loss recovery sequence if a power loss occurs during a write nonvolatile configuration register command, after the next power-on, the device might begin in an undetermined state (xip mode or an unnecessary protocol). if this occurs, until the next power-up, a recov- ery sequence must reset the device to a fixed state (extended spi protocol without xip). after the recovery sequence, the issue should be resolved definitively by running the write nonvolatile configuration register command again. the recovery se- quence is composed of two parts that must be run in the correct order. during the en- tire sequence, t shsl2 must be at least 50ns. the first part of the sequence is dq0 (pad data) and dq3 (pad hold) equal to 1 for the situations listed below: ? 7 clock cycles within s# low (s# becomes high before 8th clock cycle) ? + 9 clock cycles within s# low (s# becomes high before 10th clock cycle) ? + 13 clock cycles within s# low (s# becomes high before 14th clock cycle) ? + 17 clock cycles within s# low (s# becomes high before 18th clock cycle) ? + 25 clock cycles within s# low (s# becomes high before 26th clock cycle) ? + 33 clock cycles within s# low (s# becomes high before 34th clock cycle) the second part of the sequence is exiting from dual or quad spi protocol by using the following ffh sequence: dq0 and dq3 equal to 1 for 8 clock cycles within s# low; s# becomes high before 9th clock cycle. after this two-part sequence the extended spi protocol is active. 512mb, multiple i/o serial flash memory power-up and power-down pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 75 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
ac reset specifications table 34: ac reset conditions note 1 applies to entire table parameter symbol conditions min typ max unit reset pulse width t rlrh 2 50 C C ns reset recovery time t rhsl device deselected (s# high) and is in xip mode C C 40 ns device deselected (s# high) and is in standby mode C C 40 ns commands are being decoded, any read operations are in progress or any write operation to volatile registers are in progress C C 40 ns any device array program/erase/suspend/resume, program otp, nonvolatile sector lock, and erase nonvolatile sector lock array operations are in progress C C 30 s while a write status register operation is in progress C t w C ms while a write nonvolatile configuration regis- ter operation is in progress C t wnvcr C ms on completion or suspension of a subsector erase op- eration C t sse C s software reset recovery time t shsl3 device deselected (s# high) and is in standby mode C C 40 ns any flash array program/erase/suspend/resume, program otp, nonvolatile sector lock, and erase nonvolatile sector lock array operations are in progress C C 30 s while write status register operation is in progress C t w C ms while a write nonvolatile configuration regis- ter operation is in progress C t wnvcr C ms on completion or suspension of a subsector erase op- eration C t sse C s s# deselect to reset valid t shrv deselect to reset valid in quad output or in qio-spi 2 C C ns notes: 1. values are guaranteed by characterization; not 100% tested. 2. the device reset is possible but not guaranteed if t rlrh < 50ns. 512mb, multiple i/o serial flash memory ac reset specifications pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 76 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 39: reset ac timing during program or erase cycle t shrh t rlrh t rhsl s# reset# dont care figure 40: reset enable c s# dq0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 reset enable reset memory t shsl2 t shsl3 figure 41: serial input timing t slch t chsl t dvch t chdx t clch t chcl t chsh t shch t shsl s# c dq0 dq1 high-z high-z msb in lsb in dont care 512mb, multiple i/o serial flash memory ac reset specifications pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 77 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 42: hold timing t hlch t chhl t hhch t hlqz t chhh t hhqx s# c dq0 dq1 hold# dont care figure 43: output timing t cl t ch s# c dq0 dq1 lsb out address lsb in dont care t clqx t clqx t shqz t clqv t clqv 512mb, multiple i/o serial flash memory ac reset specifications pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 78 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 44: v pph timing s# c dq0 t vpphsl end of command (identified by wip polling) v pph v pp 512mb, multiple i/o serial flash memory ac reset specifications pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 79 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
absolute ratings and operating conditions stresses greater than those listed may cause permanent damage to the device. this is a stress rating only. exposure to absolute maximum rating for extended periods may ad- versely affect reliability. stressing the device beyond the absolute maximum ratings may cause permanent damage. table 35: absolute ratings symbol parameter min max units notes t stg storage temperature C65 150 c t lead lead temperature during soldering C see note 1 c v cc supply voltage C0.6 4.0 v v pp fast program/erase voltage C0.2 10 v v io input/output voltage with respect to ground C0.6 v cc + 0.6 v 3, 4 v esd electrostatic discharge voltage (human body model) C2000 2000 v 2 notes: 1. compliant with jedec standard j-std-020c (for small-body, sn-pb or pb assembly), rohs, and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu. 2. jedec standard jesd22-a114a (c1 = 100pf, r1 = 1500 , r2 = 500 ). 3. during signal transitions, minimum voltage may undershoot to C1v for periods less than 10ns. 4. during signal transitions, maximum voltage may overshoot to v cc + 1v for periods less than 10ns. table 36: operating conditions symbol parameter min max units v cc supply voltage 2.7 3.6 v v pph supply voltage on v pp 8.5 9.5 v t a ambient operating temperature C40 85 c table 37: input/output capacitance note 1 applies to entire table symbol description test condition min max units c in/out input/output capacitance (dq0/dq1/dq2/dq3) v out = 0v C 8 pf c in input capacitance (other pins) v in = 0v C 6 pf note: 1. these parameters are sampled only, not 100% tested. t a = 25c at 54 mhz. 512mb, multiple i/o serial flash memory absolute ratings and operating conditions pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 80 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 38: ac timing input/output conditions symbol description min max units notes c l load capacitance 30 30 pf 1 C input rise and fall times C 5 ns input pulse voltages 0.2v cc to 0.8v cc v 2 input timing reference voltages 0.3v cc to 0.7v cc v output timing reference voltages v cc /2 v cc /2 v notes: 1. output buffers are configurable by user. 2. for quad/dual operations: 0v to v cc . figure 45: ac timing input/output reference levels 0.8v cc 0.2v cc 0.7v cc 0.5v cc 0.3v cc input levels 1 i/o timing reference levels note: 1. 0.8v cc = v cc for dual/quad operations; 0.2v cc = 0v for dual/quad operations. 512mb, multiple i/o serial flash memory absolute ratings and operating conditions pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 81 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
dc characteristics and operating conditions table 39: dc current characteristics and operating conditions parameter symbol test conditions min max unit input leakage current i li C 2 a output leakage current i lo C 2 a standby current i cc1 s = v cc , v in = v ss or v cc C 150 a standby current i cc1 (automotive) 1 s = v cc , v in = v ss or v cc C 300 a operating current (fast-read extended i/o) i cc3 c = 0.1v cc /0.9v cc at 108 mhz, dq1 = open C 15 ma c = 0.1v cc /0.9v cc at 54 mhz, dq1 = open C 6 ma operating current (fast-read dual i/o) c = 0.1v cc /0.9v cc at 108 mhz C 18 ma operating current (fast-read quad i/o) c = 0.1v cc /0.9v cc at 108 mhz C 20 ma operating current (program) i cc4 s# = v cc C 20 ma operating current (write status regis- ter) i cc5 s# = v cc C 20 ma operating current (erase) i cc6 s# = v cc C 20 ma note: 1. automotive temperature range = C40c to 125c; see also the part number information table. table 40: dc voltage characteristics and operating conditions parameter symbol conditions min max unit input low voltage v il C0.5 0.3v cc v input high voltage v ih 0.7v cc v cc + 0.4 v output low voltage v ol i ol = 1.6ma C 0.4 v output high voltage v oh i oh = C100a v cc - 0.2 C v 512mb, multiple i/o serial flash memory dc characteristics and operating conditions pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 82 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
ac characteristics and operating conditions table 41: ac characteristics and operating conditions parameter symbol min typ 1 max unit notes clock frequency for all commands other than read (spi-er, qio-spi protocol) f c dc C 108 mhz clock frequency for read commands f r dc C 54 mhz clock high time t ch 4 C C ns 2 clock low time t cl 4 C C ns 1 clock rise time (peak-to-peak) t clch 0.1 C C v/ns 3, 4 clock fall time (peak-to-peak) t chcl 0.1 C C v/ns 3, 4 s# active setup time (relative to clock) t slch 4 C C ns s# not active hold time (relative to clock) t chsl 4 C C ns data in setup time t dvch 2 C C ns data in hold time t chdx 3 C C ns s# active hold time (relative to clock) t chsh 4 C C ns s# not active setup time (relative to clock) t shch 4 C C ns s# deselect time after a read command t shsl1 20 C C ns s# deselect time after a nonread command t shsl2 50 C C ns output disable time t shqz C C 8 ns 3 clock low to output valid under 30pf str t clqv C C 7 ns dtr C C 8 ns clock low to output valid under 10pf str C C 5 ns dtr C C 6 ns output hold time (clock low) t clqx 1 C C ns output hold time (clock high) t chqx 1 C C ns hold command setup time (relative to clock) t hlch 4 C C ns hold command hold time (relative to clock) t chhh 4 C C ns hold command setup time (relative to clock) t hhch 4 C C ns hold command hold time (relative to clock) t chhl 4 C C ns hold command to output low-z t hhqx C C 8 ns 3 hold command to output high-z t hlqz C C 8 ns 3 write protect setup time t whsl 20 C C ns 5 write protect hold time t shwl 100 C C ns 5 enhanced v pph high to s# low for extended and dual i/o page program t vpphsl 200 C C ns 6 write status register cycle time t w C 1.3 8 ms write nonvolatile configuration register cycle time t wnvcr C 0.2 3 s clear flag status register cycle time t cfsr C 40 C ns 512mb, multiple i/o serial flash memory ac characteristics and operating conditions pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 83 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 41: ac characteristics and operating conditions (continued) parameter symbol min typ 1 max unit notes write volatile configuration register cycle time t wvcr C 40 C ns write volatile enhanced configuration register cycle time t wrvecr C 40 C ns write extended address register cycle time t wrear C 40 C ns page program cycle time (256 bytes) t pp C 0.5 5 ms 7 page program cycle time ( n bytes) C int(n/8) 0.015 8 5 ms 7 page program cycle time, v pp = v pph ( 256 bytes) C 0.4 5 ms 7 program otp cycle time (64 bytes) C 0.2 C ms 7 subsector erase cycle time t sse C 0.25 0.8 s sector erase cycle time t se C 0.7 3 s sector erase cycle time (with v pp = v pph ) C 0.6 3 s die erase/bulk erase cycle time t be C 240 480 s 9 die erase/bulk erase cycle time (with v pp = v pph ) C 200 480 s 9 notes: 1. typical values given for t a = 25 c. 2. t ch + t cl must add up to 1/ f c. 3. value guaranteed by characterization; not 100% tested. 4. expressed as a slew-rate. 5. only applicable as a constraint for a write status register command when status register write is set to 1. 6. v pph should be kept at a valid level until the program or erase operation has comple- ted and its result (success or failure) is known. 7. when using the page program command to program consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes (1 < n < 256). 8. int(a) corresponds to the upper integer part of a. for example int(12/8) = 2, int(32/8) = 4 int(15.3) =16. 9. bulk erase command only available for part numbers n25q512a83gsf40x and n25q512a83g1240x. 512mb, multiple i/o serial flash memory ac characteristics and operating conditions pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 84 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
package dimensions figure 46: v-pdfn-8/8mm x 6mm 8.00 typ 6.00 typ 4.80 typ 5.16 typ 0.2 min 0.40 0.05 pin 1 id ?0.3 1.27 typ 0.05 max 0.40 +0.08 -0.05 0.85 typ/ 1 max pin 1 id r 0.20 0.05 c 0.10 c m 0.10 c a b 0.15 c a b 0.15 c m 0.05 c (ne - 1) 1.27 typ 8 7 6 5 1 2 3 4 notes: 1. all dimensions are in millimeters. 2. see part number ordering information for complete package names and details. 512mb, multiple i/o serial flash memory package dimensions pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 85 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 47: sop2-16/300 mils 16 0.23 min/ 0.32 max 1 8 9 0.40 min/ 1.27 max 0.20 0.1 2.5 0.15 10.30 0.20 7.50 0.10 10.00 min/ 10.65 max 0.33 min/ 0.51 max 0.1 z 0 min/8 max 1.27 typ h x 45 z notes: 1. all dimensions are in millimeters. 2. see part number ordering information for complete package names and details. 512mb, multiple i/o serial flash memory package dimensions pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 86 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 48: t-pbga-24b05/6mm x 8mm ball a1 id 1.20 max 6 0.10 0.20 min 1.00 typ 1.00 typ 8 0.10 4.00 ball a1 id 4.00 0.79 typ seating plane 0.1 a a 24x ?0.40 0.05 5 4 3 2 1 a b c d e notes: 1. all dimensions are in millimeters. 2. see part number ordering information for complete package names and details. 512mb, multiple i/o serial flash memory package dimensions pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 87 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
part number ordering information micron serial nor flash devices are available in different configurations and densities. verify valid part numbers by using microns part catalog search at micron.com . to com- pare features and specifications by device type, visit micron.com/products . contact the factory for devices not found. for more information on how to identify products and top-side marking by the process identification letter, refer to technical note tn-12-24, "serial flash memory device marking for the m25p, m25pe, m25px, and n25q product families." table 42: part number information part number category category details notes device type n25q = serial nor flash memory, multiple input/output (single, dual, quad i/o), xip density 512 = 512mb technology a = 65nm feature set 1 = byte addressability; hold pin; micron xip 1 2 = byte addressability; hold pin; basic xip 1 3 = byte addressability; rst# pin; micron xip 1 4 = byte addressability; rst# pin; basic xip 1 7 = byte addressability; hold pin; micron xip 2 8 = byte addressability; hold pin; micron xip; reset pin 1 operating voltage 3 = v cc = 2.7 to 3.6v block structure g = uniform (64kb and 4kb) , easy transparent stack package (rohs-compliant) f8 = v-pdfn-8/8mm x 6mm rp sf = sop2-16/300mils 12 = t-pbga-24b05/6mm x 8mm 3 temperature and test flow 4 = it: C40c to 85c; device tested with standard test flow a = automotive temperature range, C40 to 125c; device tested with high reliability certified test flow h = it: C40c to 85c; device tested with high reliability certified test flow security features 0 = default 4 shipping material e = tray f = tape and reel g = tube notes: 1. enter 4-byte address mode and exit 4-byte address mode supported. 2. 4-byte addressing mode is the default at power-up. enter and exit 4-byte addressing mode are not supported. 3. see the table below for additional information. 4. additional secure options are available upon customer request. 512mb, multiple i/o serial flash memory part number ordering information pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 88 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 43: package details micron spi and jedec package name shortened package name package description m25p m45pe symbol n25q symbol m25p m45pe package names alternate package name v-pdfn-8/8mm x 6mm rp dfn-8/8mm very thin, plastic small-out- line, 8 terminal pads (no leads), 8mm x 6mm me f8 mlp8, vdfpn8 v-pson1-8/8mm x 6mm, vson sop2-16/300mil so16w small-outline integrated circuit, 16-pin, wide (300 mil) mf sf so16w, so16 wide 300 mil body width soic-16/300 mil, sop 16l 300 mil t- pbga-24b05/6x8 tbga 24 thin, plastic-ball grid array, 24-ball, 6mm x 8mm zm 12 tbga24 6x8mm t-pbga-24b05/6x8 512mb, multiple i/o serial flash memory part number ordering information pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 89 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
revision history rev. o C 05/13 ? changed icc1 (grade 3) to icc1 (automotive) in the dc current characteristics and operating conditions table, and added a footnote ? revised maximum temperature (C40c to 125c) in dc characteristics and operating conditions table footnote ? added part number n25q512a83gsf40x and n25q512a83g1240x in ac characteris- tics and operating conditions table note rev. n C 02/13 ? updated the read id operation figure in read id operations ? updated erase operations ? added link to part number chart in part number ordering information ? updated part numbers in features rev. m C 12/12 ? revised part numbers to selected notes in the command definitions table. rev. l C 11/12 ? typo fix in command set table in command definitions C dual i/o fast read - dtr from dbh to bdh rev. k C 11/12 ? updated part numbers rev. j C 08/12 ? additional command (bulk erase) added to command set table in command defi- nitions ? corrections to commands in command definitions rev. i C 07/12 ? added part number n25q512a13gsfa0x to features ? added i cc1 (grade 3) to dc characteristics and operating conditions rev. h C 06/12 ? added part numbers n25q512a83gsf40x and n25q512a83g1240x and associated quad commands for these part numbers. rev. g C 06/12 ? typo fix in supported clock frequencies - dtr table in nonvolatile and volatile reg- isters ? updated t sse specification in ac reset conditions table 512mb, multiple i/o serial flash memory revision history pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 90 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
rev. f C 06/12 ? added mlp8 ballout to signal assignments ? updated dimensions to v-pdfn-8/8mm x 6mm package in package dimensions ? typo fix in supported clock frequencies - dtr table in nonvolatile and volatile reg- isters rev. e C 05/12 ? added v-pdfn 8/8mm x 6mm package rev. d C 02/12 ? to production status rev. c, preliminary C 11/11 ? updated supported clock frequencies C str in nonvolatile and volatile registers rev. b C 11/11 ? correction to bit 1:0; a24 in description corrected to a[25:24] of extended address register bit definitions table in nonvolatile and volatile registers rev. a C 07/11 ? initial release 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 512mb, multiple i/o serial flash memory revision history pdf: 09005aef84752721 n25q_512mb_1ce_3v_65nm.pdf - rev. o 05/13 en 91 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.

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